[RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[Chunfeng Yun]

There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
index 42d8814f903a..02cba4212f7d 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
@@ -16,6 +16,7 @@ Required properties:
 	"mediatek,mtk-xhci" compatible string, you need SoC specific ones in
 	addition, one of:
 	- "mediatek,mt8173-xhci"
+	- "mediatek,mt8195-xhci"
  - reg : specifies physical base address and size of the registers
  - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
  - interrupts : interrupt used by the controller
-- 
2.18.0

[RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun]

There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz for those controllers.
Note: the first controller no need set it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix typo of comaptible
---
 drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 8f321f39ab96..0a68c4ac8b48 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -68,11 +68,71 @@
 #define SSC_IP_SLEEP_EN	BIT(4)
 #define SSC_SPM_INT_EN		BIT(1)
 
+/* xHCI csr */
+#define LS_EOF			0x930
+#define LS_EOF_OFFSET		0x89
+
+#define FS_EOF			0x934
+#define FS_EOF_OFFSET		0x2e
+
+#define SS_GEN1_EOF		0x93c
+#define SS_GEN1_EOF_OFFSET	0x78
+
+#define HFCNTR_CFG		0x944
+#define ITP_DELTA_CLK		(0xa << 1)
+#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG	(0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
+
+#define SS_GEN2_EOF		0x990
+#define SS_GEN2_EOF_OFFSET	0x3c
+#define EOF_OFFSET_MASK		GENMASK(11, 0)
+
 enum ssusb_uwk_vers {
 	SSUSB_UWK_V1 = 1,
 	SSUSB_UWK_V2,
 };
 
+/*
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M, so need change the interval.
+ */
+static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
+{
+	struct device *dev = mtk->dev;
+	struct usb_hcd *hcd = mtk->hcd;
+	u32 value;
+
+	if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
+		return;
+
+	value = readl(hcd->regs + HFCNTR_CFG);
+	value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
+	value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+	writel(value, hcd->regs + HFCNTR_CFG);
+
+	value = readl(hcd->regs + LS_EOF);
+	value &= ~EOF_OFFSET_MASK;
+	value |= LS_EOF_OFFSET;
+	writel(value, hcd->regs + LS_EOF);
+
+	value = readl(hcd->regs + FS_EOF);
+	value &= ~EOF_OFFSET_MASK;
+	value |= FS_EOF_OFFSET;
+	writel(value, hcd->regs + FS_EOF);
+
+	value = readl(hcd->regs + SS_GEN1_EOF);
+	value &= ~EOF_OFFSET_MASK;
+	value |= SS_GEN1_EOF_OFFSET;
+	writel(value, hcd->regs + SS_GEN1_EOF);
+
+	value = readl(hcd->regs + SS_GEN2_EOF);
+	value &= ~EOF_OFFSET_MASK;
+	value |= SS_GEN2_EOF_OFFSET;
+	writel(value, hcd->regs + SS_GEN2_EOF);
+}
+
 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
 {
 	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
@@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
 		ret = xhci_mtk_ssusb_config(mtk);
 		if (ret)
 			return ret;
+
+		xhci_mtk_set_frame_interval(mtk);
 	}
 
 	ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
@@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = {
 #ifdef CONFIG_OF
 static const struct of_device_id mtk_xhci_of_match[] = {
 	{ .compatible = "mediatek,mt8173-xhci"},
+	{ .compatible = "mediatek,mt8195-xhci"},
 	{ .compatible = "mediatek,mtk-xhci"},
 	{ },
 };
-- 
2.18.0

Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun]

Hi Mathias,

On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz for those controllers.
> Note: the first controller no need set it.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: fix typo of comaptible
> ---
>  drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
> 
> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
> index 8f321f39ab96..0a68c4ac8b48 100644
> --- a/drivers/usb/host/xhci-mtk.c
> +++ b/drivers/usb/host/xhci-mtk.c
> @@ -68,11 +68,71 @@
>  #define SSC_IP_SLEEP_EN	BIT(4)
>  #define SSC_SPM_INT_EN		BIT(1)
>  
Can I Read/Write the following xHCI controller's registers  in
xhci-mtk.c?

Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
glue driver used to initialize clocks/power and IPPC registers which
don't belong to xHCI controller.

Thanks

> +/* xHCI csr */
> +#define LS_EOF			0x930
> +#define LS_EOF_OFFSET		0x89
> +
> +#define FS_EOF			0x934
> +#define FS_EOF_OFFSET		0x2e
> +
> +#define SS_GEN1_EOF		0x93c
> +#define SS_GEN1_EOF_OFFSET	0x78
> +
> +#define HFCNTR_CFG		0x944
> +#define ITP_DELTA_CLK		(0xa << 1)
> +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
> +#define FRMCNT_LEV1_RANG	(0x12b << 8)
> +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
> +
> +#define SS_GEN2_EOF		0x990
> +#define SS_GEN2_EOF_OFFSET	0x3c
> +#define EOF_OFFSET_MASK		GENMASK(11, 0)
> +
>  enum ssusb_uwk_vers {
>  	SSUSB_UWK_V1 = 1,
>  	SSUSB_UWK_V2,
>  };
>  
> +/*
> + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
> + * is calculated from the frame counter clock 24M, but in fact, the clock
> + * is 48M, so need change the interval.
> + */
> +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
> +{
> +	struct device *dev = mtk->dev;
> +	struct usb_hcd *hcd = mtk->hcd;
> +	u32 value;
> +
> +	if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
> +		return;
> +
> +	value = readl(hcd->regs + HFCNTR_CFG);
> +	value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
> +	value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
> +	writel(value, hcd->regs + HFCNTR_CFG);
> +
> +	value = readl(hcd->regs + LS_EOF);
> +	value &= ~EOF_OFFSET_MASK;
> +	value |= LS_EOF_OFFSET;
> +	writel(value, hcd->regs + LS_EOF);
> +
> +	value = readl(hcd->regs + FS_EOF);
> +	value &= ~EOF_OFFSET_MASK;
> +	value |= FS_EOF_OFFSET;
> +	writel(value, hcd->regs + FS_EOF);
> +
> +	value = readl(hcd->regs + SS_GEN1_EOF);
> +	value &= ~EOF_OFFSET_MASK;
> +	value |= SS_GEN1_EOF_OFFSET;
> +	writel(value, hcd->regs + SS_GEN1_EOF);
> +
> +	value = readl(hcd->regs + SS_GEN2_EOF);
> +	value &= ~EOF_OFFSET_MASK;
> +	value |= SS_GEN2_EOF_OFFSET;
> +	writel(value, hcd->regs + SS_GEN2_EOF);
> +}
> +
>  static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
>  {
>  	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
> @@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
>  		ret = xhci_mtk_ssusb_config(mtk);
>  		if (ret)
>  			return ret;
> +
> +		xhci_mtk_set_frame_interval(mtk);
>  	}
>  
>  	ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
> @@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = {
>  #ifdef CONFIG_OF
>  static const struct of_device_id mtk_xhci_of_match[] = {
>  	{ .compatible = "mediatek,mt8173-xhci"},
> +	{ .compatible = "mediatek,mt8195-xhci"},
>  	{ .compatible = "mediatek,mtk-xhci"},
>  	{ },
>  };

Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Mathias Nyman]

On 7.2.2021 4.27, Chunfeng Yun wrote:
> Hi Mathias,
> 
> On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
>> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
>> exclude IP0) have a wrong default SOF/ITP interval which is
>> calculated from the frame counter clock 24Mhz by default, but
>> in fact, the frame counter clock is 48Mhz, so we should set
>> the accurate interval according to 48Mhz for those controllers.
>> Note: the first controller no need set it.
>>
>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
>> ---
>> v2: fix typo of comaptible
>> ---
>>  drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
>>  1 file changed, 63 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
>> index 8f321f39ab96..0a68c4ac8b48 100644
>> --- a/drivers/usb/host/xhci-mtk.c
>> +++ b/drivers/usb/host/xhci-mtk.c
>> @@ -68,11 +68,71 @@
>>  #define SSC_IP_SLEEP_EN	BIT(4)
>>  #define SSC_SPM_INT_EN		BIT(1)
>>  
> Can I Read/Write the following xHCI controller's registers  in
> xhci-mtk.c?
> 
> Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
> glue driver used to initialize clocks/power and IPPC registers which
> don't belong to xHCI controller.
> 

These *_EOF registers look like they are Mediatek vendor specific registers
and not part of public xHCI register-level spec. 
So I think accessing them from xhci-mtk.c makes sense.

If those register offsets are hardcoded like this in the Mediatek spec then
this is fine, but if those offsets are found from a vendor specific xHCI
extended capability entry (see xhci spec section 7) then we should dig them out
from there. 
>> +/* xHCI csr */
>> +#define LS_EOF			0x930
>> +#define LS_EOF_OFFSET		0x89
>> +
>> +#define FS_EOF			0x934
>> +#define FS_EOF_OFFSET		0x2e
>> +
>> +#define SS_GEN1_EOF		0x93c
>> +#define SS_GEN1_EOF_OFFSET	0x78
>> +
>> +#define HFCNTR_CFG		0x944
>> +#define ITP_DELTA_CLK		(0xa << 1)
>> +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
>> +#define FRMCNT_LEV1_RANG	(0x12b << 8)
>> +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
>> +
>> +#define SS_GEN2_EOF		0x990
>> +#define SS_GEN2_EOF_OFFSET	0x3c
>> +#define EOF_OFFSET_MASK		GENMASK(11, 0)
>> +
>>  enum ssusb_uwk_vers {
>>  	SSUSB_UWK_V1 = 1,
>>  	SSUSB_UWK_V2,
>>  };
>>  
>> +/*
>> + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
>> + * is calculated from the frame counter clock 24M, but in fact, the clock
>> + * is 48M, so need change the interval.
>> + */
>> +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
>> +{
>> +	struct device *dev = mtk->dev;
>> +	struct usb_hcd *hcd = mtk->hcd;
>> +	u32 value;
>> +
>> +	if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
>> +		return;
>> +
>> +	value = readl(hcd->regs + HFCNTR_CFG);
>> +	value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
>> +	value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
>> +	writel(value, hcd->regs + HFCNTR_CFG);
>> +
>> +	value = readl(hcd->regs + LS_EOF);
>> +	value &= ~EOF_OFFSET_MASK;
>> +	value |= LS_EOF_OFFSET;
>> +	writel(value, hcd->regs + LS_EOF);
>> +
>> +	value = readl(hcd->regs + FS_EOF);
>> +	value &= ~EOF_OFFSET_MASK;
>> +	value |= FS_EOF_OFFSET;
>> +	writel(value, hcd->regs + FS_EOF);
>> +
>> +	value = readl(hcd->regs + SS_GEN1_EOF);
>> +	value &= ~EOF_OFFSET_MASK;
>> +	value |= SS_GEN1_EOF_OFFSET;
>> +	writel(value, hcd->regs + SS_GEN1_EOF);
>> +
>> +	value = readl(hcd->regs + SS_GEN2_EOF);
>> +	value &= ~EOF_OFFSET_MASK;
>> +	value |= SS_GEN2_EOF_OFFSET;
>> +	writel(value, hcd->regs + SS_GEN2_EOF);

Minor nit about names,
Register offsets from MMIO start are named *_EOF while clock multipliers? are named *_EOF_OFFSET.
This was a bit confusing

Thanks
-Mathias

Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun]

On Mon, 2021-02-08 at 13:43 +0200, Mathias Nyman wrote:
> On 7.2.2021 4.27, Chunfeng Yun wrote:
> > Hi Mathias,
> > 
> > On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
> >> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> >> exclude IP0) have a wrong default SOF/ITP interval which is
> >> calculated from the frame counter clock 24Mhz by default, but
> >> in fact, the frame counter clock is 48Mhz, so we should set
> >> the accurate interval according to 48Mhz for those controllers.
> >> Note: the first controller no need set it.
> >>
> >> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> >> ---
> >> v2: fix typo of comaptible
> >> ---
> >>  drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 63 insertions(+)
> >>
> >> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
> >> index 8f321f39ab96..0a68c4ac8b48 100644
> >> --- a/drivers/usb/host/xhci-mtk.c
> >> +++ b/drivers/usb/host/xhci-mtk.c
> >> @@ -68,11 +68,71 @@
> >>  #define SSC_IP_SLEEP_EN	BIT(4)
> >>  #define SSC_SPM_INT_EN		BIT(1)
> >>  
> > Can I Read/Write the following xHCI controller's registers  in
> > xhci-mtk.c?
> > 
> > Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
> > glue driver used to initialize clocks/power and IPPC registers which
> > don't belong to xHCI controller.
> > 
> 
> These *_EOF registers look like they are Mediatek vendor specific registers
> and not part of public xHCI register-level spec. 
> So I think accessing them from xhci-mtk.c makes sense.
> 
> If those register offsets are hardcoded like this in the Mediatek spec then
> this is fine, 
Check it with our DE, it's this case.
> but if those offsets are found from a vendor specific xHCI
> extended capability entry (see xhci spec section 7) then we should dig them out
> from there. 
> >> +/* xHCI csr */
> >> +#define LS_EOF			0x930
> >> +#define LS_EOF_OFFSET		0x89
> >> +
> >> +#define FS_EOF			0x934
> >> +#define FS_EOF_OFFSET		0x2e
> >> +
> >> +#define SS_GEN1_EOF		0x93c
> >> +#define SS_GEN1_EOF_OFFSET	0x78
> >> +
> >> +#define HFCNTR_CFG		0x944
> >> +#define ITP_DELTA_CLK		(0xa << 1)
> >> +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
> >> +#define FRMCNT_LEV1_RANG	(0x12b << 8)
> >> +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
> >> +
> >> +#define SS_GEN2_EOF		0x990
> >> +#define SS_GEN2_EOF_OFFSET	0x3c
> >> +#define EOF_OFFSET_MASK		GENMASK(11, 0)
> >> +
> >>  enum ssusb_uwk_vers {
> >>  	SSUSB_UWK_V1 = 1,
> >>  	SSUSB_UWK_V2,
> >>  };
> >>  
> >> +/*
> >> + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
> >> + * is calculated from the frame counter clock 24M, but in fact, the clock
> >> + * is 48M, so need change the interval.
> >> + */
> >> +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
> >> +{
> >> +	struct device *dev = mtk->dev;
> >> +	struct usb_hcd *hcd = mtk->hcd;
> >> +	u32 value;
> >> +
> >> +	if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
> >> +		return;
> >> +
> >> +	value = readl(hcd->regs + HFCNTR_CFG);
> >> +	value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
> >> +	value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
> >> +	writel(value, hcd->regs + HFCNTR_CFG);
> >> +
> >> +	value = readl(hcd->regs + LS_EOF);
> >> +	value &= ~EOF_OFFSET_MASK;
> >> +	value |= LS_EOF_OFFSET;
> >> +	writel(value, hcd->regs + LS_EOF);
> >> +
> >> +	value = readl(hcd->regs + FS_EOF);
> >> +	value &= ~EOF_OFFSET_MASK;
> >> +	value |= FS_EOF_OFFSET;
> >> +	writel(value, hcd->regs + FS_EOF);
> >> +
> >> +	value = readl(hcd->regs + SS_GEN1_EOF);
> >> +	value &= ~EOF_OFFSET_MASK;
> >> +	value |= SS_GEN1_EOF_OFFSET;
> >> +	writel(value, hcd->regs + SS_GEN1_EOF);
> >> +
> >> +	value = readl(hcd->regs + SS_GEN2_EOF);
> >> +	value &= ~EOF_OFFSET_MASK;
> >> +	value |= SS_GEN2_EOF_OFFSET;
> >> +	writel(value, hcd->regs + SS_GEN2_EOF);
> 
> Minor nit about names,
> Register offsets from MMIO start are named *_EOF while clock multipliers? are named *_EOF_OFFSET.
> This was a bit confusing
Good point, the names come from register map docs, I'll modify it,
thanks a lot
> 
> Thanks
> -Mathias

[RFC PATCH v2 3/3] arm64: dts: mt8195: add USB related nodes

[Chunfeng Yun]

Add USB nodes, PHY nodes and some fixed regulator nodes.
We prefer to use mt8192's compatible for the first USB controller
(port0), there is no wrong with the SOF/ITP interval; but for other
controllers (port1~port3) should use mt8195's one due to the wrong
default setting of SOF/ITP interval which should be calculated from
48M, but not 24M by default.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 arch/arm64/boot/dts/mediatek/mt8195-evb.dts |  70 +++++++++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi    | 163 ++++++++++++++++++++
 2 files changed, 233 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index 7264232bb7e9..a60682752e19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 #include "mt8195.dtsi"
 #include "mt6359.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "MediaTek MT8195 evaluation board";
@@ -49,6 +50,36 @@
 	        enable-active-high;
 	        regulator-always-on;
 	};
+
+	usb_p0_vbus: regulator@2 {
+		compatible = "regulator-fixed";
+		gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vbus0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	usb_p2_vbus: regulator@3 {
+		compatible = "regulator-fixed";
+		gpio = <&pio 131 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vbus2";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	usb_p3_vbus: regulator@4 {
+		compatible = "regulator-fixed";
+		gpio = <&pio 5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vbus3";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+	};
 };
 
 &pmic {
@@ -156,6 +187,22 @@
 	status = "okay";
 };
 
+&u3phy0 {
+	status="okay";
+};
+
+&u3phy1 {
+	status = "okay";
+};
+
+&u3phy2 {
+	status="okay";
+};
+
+&u3phy3 {
+	status="okay";
+};
+
 &pio {
 	nor_pins_default: nordefault {
 		pins0 {
@@ -311,3 +358,26 @@
 	};
 };
 
+
+&xhci0 {
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	vbus-supply = <&usb_p0_vbus>;
+	status = "okay";
+};
+
+&xhci1 {
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	status = "okay";
+};
+
+&xhci2 {
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	vbus-supply = <&usb_p2_vbus>;
+	status = "okay";
+};
+
+&xhci3 {
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	vbus-supply = <&usb_p3_vbus>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index ccb9d24b1c1e..60c75b23cf03 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8195-memory-port.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/power/mt8195-power.h>
 #include <dt-bindings/reset/ti-syscon.h>
@@ -914,6 +915,83 @@
 			status = "disabled";
 		};
 
+		xhci0: usb@11200000 {
+			compatible = "mediatek,mt8192-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			status = "disabled";
+		};
+
+		xhci1: usb@11290000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11290000 0 0x1000>,
+			      <0 0x11293e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port1 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P1_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			status = "disabled";
+		};
+
+		xhci2: usb@112a0000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x112a0000 0 0x1000>,
+			      <0 0x112a3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port2 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			status = "disabled";
+		};
+
+		xhci3: usb@112b0000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x112b0000 0 0x1000>,
+			      <0 0x112b3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port3 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			status = "disabled";
+		};
+
 		pcie0: pcie@112f0000 {
 			device_type = "pci";
 			compatible = "mediatek,mt8195-pcie";
@@ -998,6 +1076,40 @@
 			status = "disabled";
 		};
 
+		u3phy2: usb-phy2@11c40000 {
+			compatible = "mediatek,mt8195-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11c40000 0x700>;
+			status = "disabled";
+
+			u2port2: usb2-phy2@0 {
+				reg = <0 0x700>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "disabled";
+			};
+		};
+
+		u3phy3: usb-phy3@11c50000 {
+			compatible = "mediatek,mt8195-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11c50000 0x700>;
+			status = "disabled";
+
+			u2port3: usb2-phy3@0 {
+				reg = <0 0x700>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
 		i2c5: i2c5@11d00000 {
 			compatible = "mediatek,mt8195-i2c",
 				"mediatek,mt8192-i2c";
@@ -1138,6 +1250,57 @@
 			#clock-cells = <1>;
 		};
 
+		u3phy1: usb-phy1@11e30000 {
+			compatible = "mediatek,mt8195-tphy",
+				     "mediatek,generic-tphy-v2";
+			power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11e30000 0x1000>;
+			status = "disabled";
+
+			u2port1: usb2-phy1@0 {
+				reg = <0 0x700>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+
+			u3port1: usb3-phy1@700 {
+				reg = <0x700 0x900>;
+				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
+		u3phy0: usb-phy0@11e40000 {
+			compatible = "mediatek,mt8195-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11e40000 0x1000>;
+			status = "disabled";
+
+			u2port0: usb2-phy0@0 {
+				reg = <0x0 0x700>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+
+			u3port0: usb3-phy0@700 {
+				reg = <0x700 0 0x900>;
+				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
 		pciephy: phy@11e80000 {
 			compatible = "mediatek,mt8195-pcie-phy";
 			#address-cells = <2>;
-- 
2.18.0

Re: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[Greg Kroah-Hartman]

On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes

Note, I do not apply patches with "RFC" as obviously you do not think
they are worthy of being applied.  I don't see what you are asking to be
done with this set of patches, please explain?

thanks,

greg k-h

Re: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[Chunfeng Yun]

On Wed, 2021-02-03 at 11:31 +0100, Greg Kroah-Hartman wrote:
> On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> > There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> > exclude IP0) have a wrong default SOF/ITP interval which is
> > calculated from the frame counter clock 24Mhz by default, but
> > in fact, the frame counter clock is 48Mhz, so we should set
> > the accurate interval according to 48Mhz. Here add a new compatible
> > for MT8195, it's also supported in driver. But the first controller
> > (IP0) has no such issue, we prefer to use generic compatible,
> > e.g. mt8192's compatible.
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: no changes
> 
> Note, I do not apply patches with "RFC" as obviously you do not think
> they are worthy of being applied.  I don't see what you are asking to be
> done with this set of patches, please explain?
The DTS patch [2/3] in the series will cause merge conflict, due to the
dependent patches are not upstreamed.

Another problem is that I wander to know whether the compatible usage as
following is allowed:

arch/arm64/boot/dts/mediatek/mt8195.dtsi

   usb@11200000 {  // ip0
        compatible = "mediatek,mt8192-xhci",  // here use mt8192's
compatible, avoid changing SOF/ITP interval for ip0, because it's
default value is ok."mediatek,mt8192-xhci" is not supported in driver,
so finally will use generic copatible "mediatek,mtk-xhci".

                     "mediatek,mtk-xhci";
        ....
    };

   usb@11290000 {  // ip1
        compatible = "mediatek,mt8195-xhci",  // here use mt8195's
compatible, used to change SOF/ITP interval, due the the wrong default
value.
                     "mediatek,mtk-xhci";
   };

   usb@112a0000 {  // ip2
        compatible = "mediatek,mt8195-xhci",  // same as ip1
                     "mediatek,mtk-xhci";
    };

Thank you

> 
> thanks,
> 
> greg k-h

Re: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[Greg Kroah-Hartman]

On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes

Note, I do not apply patches that have "RFC" as that means you do not
feel comfortable with them being applied.

Please resend without that when you feel they are ready to be merged.

thanks,

greg k-h

Re: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

[Rob Herring]

On Wed, 03 Feb 2021 18:26:40 +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes
> ---
>  Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>