From: Florian Fainelli <f.fainelli@gmail.com>
To: devicetree@vger.kernel.org
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
"Damien Le Moal" <damien.lemoal@opensource.wdc.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM
BCM7XXX ARM ARCHITECTURE),
"Gregory Fong" <gregory.0xf0@gmail.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Marc Zyngier" <maz@kernel.org>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
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and Parallel ATA drivers)),
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GENERATOR CORE),
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SUBSYSTEM), linux-pm@vger.kernel.org (open list:THERMAL),
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Subject: [PATCH v3 07/15] dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML
Date: Tue, 7 Dec 2021 16:37:18 -0800 [thread overview]
Message-ID: <20211208003727.3596577-8-f.fainelli@gmail.com> (raw)
In-Reply-To: <20211208003727.3596577-1-f.fainelli@gmail.com>
Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree
binding to YAML to help with validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../brcm,bcm7120-l2-intc.txt | 88 -------------
.../brcm,bcm7120-l2-intc.yaml | 123 ++++++++++++++++++
2 files changed, 123 insertions(+), 88 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
deleted file mode 100644
index addd86b6ca2f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Broadcom BCM7120-style Level 2 interrupt controller
-
-This interrupt controller hardware is a second level interrupt controller that
-is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
-platforms. It can be found on BCM7xxx products starting with BCM7120.
-
-Such an interrupt controller has the following hardware design:
-
-- outputs multiple interrupts signals towards its interrupt controller parent
-
-- controls how some of the interrupts will be flowing, whether they will
- directly output an interrupt signal towards the interrupt controller parent,
- or if they will output an interrupt signal at this 2nd level interrupt
- controller, in particular for UARTs
-
-- has one 32-bit enable word and one 32-bit status word
-
-- no atomic set/clear operations
-
-- not all bits within the interrupt controller actually map to an interrupt
-
-The typical hardware layout for this controller is represented below:
-
-2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
-
-0 -----[ MUX ] ------------|==========> GIC interrupt 75
- \-----------\
- |
-1 -----[ MUX ] --------)---|==========> GIC interrupt 76
- \------------|
- |
-2 -----[ MUX ] --------)---|==========> GIC interrupt 77
- \------------|
- |
-3 ---------------------|
-4 ---------------------|
-5 ---------------------|
-7 ---------------------|---|===========> GIC interrupt 66
-9 ---------------------|
-10 --------------------|
-11 --------------------/
-
-6 ------------------------\
- |===========> GIC interrupt 64
-8 ------------------------/
-
-12 ........................ X
-13 ........................ X (not connected)
-..
-31 ........................ X
-
-Required properties:
-
-- compatible: should be "brcm,bcm7120-l2-intc"
-- reg: specifies the base physical address and size of the registers
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
- are wired to this 2nd level interrupt controller, and how they match their
- respective interrupt parents. Should match exactly the number of interrupts
- specified in the 'interrupts' property.
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
- have a mux gate, typically UARTs. Setting these bits will make their
- respective interrupt outputs bypass this 2nd level interrupt controller
- completely; it is completely transparent for the interrupt controller
- parent. This should have one 32-bit word per enable/status pair.
-
-Example:
-
-irq0_intc: interrupt-controller@f0406800 {
- compatible = "brcm,bcm7120-l2-intc";
- interrupt-parent = <&intc>;
- #interrupt-cells = <1>;
- reg = <0xf0406800 0x8>;
- interrupt-controller;
- interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
- brcm,int-map-mask = <0xeb8>, <0x140>;
- brcm,int-fwd-mask = <0x7>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
new file mode 100644
index 000000000000..e0c6dce40d13
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7120-style Level 2 interrupt controller
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+description: >
+ This interrupt controller hardware is a second level interrupt controller that
+ is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+ platforms. It can be found on BCM7xxx products starting with BCM7120.
+
+ Such an interrupt controller has the following hardware design:
+
+ - outputs multiple interrupts signals towards its interrupt controller parent
+
+ - controls how some of the interrupts will be flowing, whether they will
+ directly output an interrupt signal towards the interrupt controller parent,
+ or if they will output an interrupt signal at this 2nd level interrupt
+ controller, in particular for UARTs
+
+ - has one 32-bit enable word and one 32-bit status word
+
+ - no atomic set/clear operations
+
+ - not all bits within the interrupt controller actually map to an interrupt
+
+ The typical hardware layout for this controller is represented below:
+
+ 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
+
+ 0 -----[ MUX ] ------------|==========> GIC interrupt 75
+ \-----------\
+ |
+ 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+ \------------|
+ |
+ 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+ \------------|
+ |
+ 3 ---------------------|
+ 4 ---------------------|
+ 5 ---------------------|
+ 7 ---------------------|---|===========> GIC interrupt 66
+ 9 ---------------------|
+ 10 --------------------|
+ 11 --------------------/
+
+ 6 ------------------------\
+ |===========> GIC interrupt 64
+ 8 ------------------------/
+
+ 12 ........................ X
+ 13 ........................ X (not connected)
+ ..
+ 31 ........................ X
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm7120-l2-intc
+
+ reg:
+ description: >
+ Specifies the base physical address and size of the registers
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts: true
+
+ "brcm,int-map-mask":
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: >
+ 32-bits bit mask describing how many and which interrupts are wired to
+ this 2nd level interrupt controller, and how they match their respective
+ interrupt parents. Should match exactly the number of interrupts
+ specified in the 'interrupts' property.
+
+ brcm,irq-can-wake:
+ type: boolean
+ description: >
+ If present, this means the L2 controller can be used as a wakeup source
+ for system suspend/resume.
+
+ brcm,int-fwd-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ if present, a bit mask to configure the interrupts which have a mux gate,
+ typically UARTs. Setting these bits will make their respective interrupt
+ outputs bypass this 2nd level interrupt controller completely; it is
+ completely transparent for the interrupt controller parent. This should
+ have one 32-bit word per enable/status pair.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+examples:
+ - |
+ irq0_intc: interrupt-controller@f0406800 {
+ compatible = "brcm,bcm7120-l2-intc";
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <1>;
+ reg = <0xf0406800 0x8>;
+ interrupt-controller;
+ interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+ brcm,int-map-mask = <0xeb8>, <0x140>;
+ brcm,int-fwd-mask = <0x7>;
+ };
--
2.25.1
next prev parent reply other threads:[~2021-12-08 0:38 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 0:37 [PATCH v3 00/15] Broadcom DT bindings updates to YAML Florian Fainelli
2021-12-08 0:37 ` [PATCH v3 01/15] dt-bindings: mmc: Convert Broadcom STB SDHCI binding " Florian Fainelli
2022-01-05 16:39 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 02/15] dt-bindings: reset: Convert Broadcom STB reset " Florian Fainelli
2021-12-09 9:41 ` Philipp Zabel
2021-12-09 23:25 ` Florian Fainelli
2021-12-14 17:47 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 03/15] dt-bindings: pwm: Convert BCM7038 PWM binding " Florian Fainelli
2021-12-14 17:47 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 04/15] dt-bindings: rtc: Convert Broadcom STB waketimer " Florian Fainelli
2021-12-14 18:00 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 05/15] dt-bindings: gpio: Convert Broadcom STB GPIO " Florian Fainelli
2021-12-10 1:44 ` Linus Walleij
2021-12-10 15:22 ` Bartosz Golaszewski
2021-12-14 18:02 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 06/15] dt-binding: interrupt-controller: Convert BCM7038 L1 intc " Florian Fainelli
2021-12-14 18:04 ` Rob Herring
2021-12-08 0:37 ` Florian Fainelli [this message]
2021-12-14 18:06 ` [PATCH v3 07/15] dt-bindings: interrupt-controller: Convert BCM7120 L2 " Rob Herring
2021-12-08 0:37 ` [PATCH v3 08/15] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 Florian Fainelli
2021-12-08 0:37 ` [PATCH v3 09/15] dt-bindings: interrupt-controller: Convert Broadcom STB L2 to YAML Florian Fainelli
2021-12-14 18:14 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 10/15] dt-bindings: rng: Convert iProc RNG200 " Florian Fainelli
2021-12-14 18:17 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 11/15] dt-bindings: thermal: Convert Broadcom TMON " Florian Fainelli
2021-12-14 18:18 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 12/15] ARM: dts: NSP: Rename SATA unit name Florian Fainelli
2021-12-08 1:23 ` Damien Le Moal
2021-12-08 0:37 ` [PATCH v3 13/15] dt-bindings: ata: Convert Broadcom SATA to YAML Florian Fainelli
2021-12-08 13:44 ` Rob Herring
2021-12-08 17:33 ` Florian Fainelli
2021-12-14 18:28 ` Rob Herring
2021-12-14 19:10 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 14/15] dt-bindings: bus: Convert GISB arbiter " Florian Fainelli
2021-12-14 19:14 ` Rob Herring
2021-12-08 0:37 ` [PATCH v3 15/15] dt-bindings: usb: Convert BDC " Florian Fainelli
2021-12-14 19:16 ` Rob Herring
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