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From: Robert Hancock <robert.hancock@calian.com>
To: linux-usb@vger.kernel.org
Cc: Thinh.Nguyen@synopsys.com, robh+dt@kernel.org,
	devicetree@vger.kernel.org, michal.simek@xilinx.com,
	balbi@kernel.org, gregkh@linuxfoundation.org,
	mounika.grace.akula@xilinx.com, manish.narani@xilinx.com,
	Robert Hancock <robert.hancock@calian.com>
Subject: [PATCH v4 1/5] usb: dwc3: xilinx: Fix PIPE clock selection for USB2.0 mode
Date: Thu, 13 Jan 2022 22:42:26 -0600	[thread overview]
Message-ID: <20220114044230.2677283-2-robert.hancock@calian.com> (raw)
In-Reply-To: <20220114044230.2677283-1-robert.hancock@calian.com>

It appears that the PIPE clock should not be selected when only USB 2.0
is being used in the design and no USB 3.0 reference clock is used. Fix
to set the correct value depending on whether a USB3 PHY is present.

Fixes: 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/usb/dwc3/dwc3-xilinx.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index 9cc3ad701a29..3bc035376394 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -167,8 +167,11 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
 	/* Set PIPE Power Present signal in FPD Power Present Register*/
 	writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
 
-	/* Set the PIPE Clock Select bit in FPD PIPE Clock register */
-	writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
+	/* Set the PIPE Clock Select bit in FPD PIPE Clock register if a USB3
+	 * PHY is in use, deselect otherwise
+	 */
+	writel(usb3_phy ? PIPE_CLK_SELECT : PIPE_CLK_DESELECT,
+	       priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
 
 	ret = reset_control_deassert(crst);
 	if (ret < 0) {
-- 
2.31.1


  reply	other threads:[~2022-01-14  4:43 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-14  4:42 [PATCH v4 0/5] Xilinx ZynqMP USB fixes Robert Hancock
2022-01-14  4:42 ` Robert Hancock [this message]
2022-01-14  4:42 ` [PATCH v4 2/5] usb: dwc3: xilinx: Fix error handling when getting USB3 PHY Robert Hancock
2022-01-14  4:42 ` [PATCH v4 3/5] dt-bindings: usb: dwc3: add reference clock period fractional adjustment Robert Hancock
2022-01-14  4:42 ` [PATCH v4 4/5] usb: dwc3: add reference clock FLADJ configuration Robert Hancock
2022-01-14 18:05   ` Sean Anderson
2022-01-14 19:22     ` Robert Hancock
2022-01-14 19:56       ` Sean Anderson
2022-01-14  4:42 ` [PATCH v4 5/5] arm64: dts: zynqmp: Add DWC3 USB reference clock period configuration Robert Hancock

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