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Thu, 5 Aug 2021 13:06:30 +0000 Subject: Re: [PATCH v2 2/4] thunderbolt: Handle ring interrupt by reading intr status To: Mika Westerberg , Sanjay R Mehta Cc: andreas.noever@gmail.com, michael.jamet@intel.com, YehezkelShB@gmail.com, Basavaraj.Natikar@amd.com, linux-usb@vger.kernel.org References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> <1627994096-99972-3-git-send-email-Sanju.Mehta@amd.com> From: Sanjay R Mehta Message-ID: <27bbe268-fd1f-8a72-7ba2-76eb82d3185e@amd.com> Date: Thu, 5 Aug 2021 18:36:17 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MA1PR01CA0102.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::18) To DM4PR12MB5103.namprd12.prod.outlook.com (2603:10b6:5:392::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.136.44.125] (165.204.157.251) by MA1PR01CA0102.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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>>> >>> +static void check_and_clear_intr_status(struct tb_ring *ring) >>> +{ >>> + if (!(ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)) { >>> + if (ring->is_tx) >>> + ioread32(ring->nhi->iobase >>> + + REG_RING_NOTIFY_BASE); >>> + else >>> + ioread32(ring->nhi->iobase >>> + + REG_RING_NOTIFY_BASE >>> + + 4 * (ring->nhi->hop_count / 32)); >>> + } >>> +} >> >> I'm now playing with this series on Intel hardware. I wanted to check >> from you whether the AMD controller implements the Auto-Clear feature? I >> mean if we always clear bit 17 of the Host Interface Control register do >> you still need to call the above or it is cleared automatically? >> >> I'm hoping that we could make this work on all controllers without too >> many special cases ;-) > > I mean if you replace patches 1 and 2 in this series with the below, > does it work with the AMD controller too? > Actually, it wont work on AMD controller because explicit read operation of interrupt status is required to clear it. > diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c > index fa44332845a1..8a5656fb956f 100644 > --- a/drivers/thunderbolt/nhi.c > +++ b/drivers/thunderbolt/nhi.c > @@ -71,10 +71,14 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) > * since we already know which interrupt was triggered. > */ > misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); > - if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { > + /* Special bit for Intel */ > + if (ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL && > + !(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) > misc |= REG_DMA_MISC_INT_AUTO_CLEAR; > - iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); > - } > + /* USB4 clear the disable auto-clear bit */ > + if (misc & BIT(17)) > + misc &= ~BIT(17); > + iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); > > ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; > step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; >