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Thu, 5 Aug 2021 12:59:49 +0000 Subject: Re: [PATCH v2 2/4] thunderbolt: Handle ring interrupt by reading intr status To: Mika Westerberg , Sanjay R Mehta Cc: andreas.noever@gmail.com, michael.jamet@intel.com, YehezkelShB@gmail.com, Basavaraj.Natikar@amd.com, linux-usb@vger.kernel.org References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> <1627994096-99972-3-git-send-email-Sanju.Mehta@amd.com> From: Sanjay R Mehta Message-ID: <36665ca4-a999-39c2-2401-8dab282145fa@amd.com> Date: Thu, 5 Aug 2021 18:29:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MA1PR01CA0154.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::24) To DM4PR12MB5103.namprd12.prod.outlook.com (2603:10b6:5:392::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.136.44.125] (165.204.157.251) by MA1PR01CA0154.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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>> >> +static void check_and_clear_intr_status(struct tb_ring *ring) >> +{ >> + if (!(ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)) { >> + if (ring->is_tx) >> + ioread32(ring->nhi->iobase >> + + REG_RING_NOTIFY_BASE); >> + else >> + ioread32(ring->nhi->iobase >> + + REG_RING_NOTIFY_BASE >> + + 4 * (ring->nhi->hop_count / 32)); >> + } >> +} > > I'm now playing with this series on Intel hardware. I wanted to check > from you whether the AMD controller implements the Auto-Clear feature? I > mean if we always clear bit 17 of the Host Interface Control register do > you still need to call the above or it is cleared automatically? > Yes, AMD implements Auto-Clear and a read operation is required to clear the interrupt status. It is explicitly described in the Spec, Section "12.6.3.4.1 -> "Table 12-27. Interrupt Status" as below "If the Disable ISR Auto-Clear bit is set to 0b, then a read operation returns the current value and then clears the register to 0." > I'm hoping that we could make this work on all controllers without too > many special cases ;-) Will it be good idea to have a separate variable in "struct tb_nhi" as "nhi->is_intr_autoclr" so that we can set in the "quirk_enable_intr_auto_clr()" as required which can be used in above check_and_clear_intr_status() function instead of vendor check. >