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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id r9sm1452666eju.74.2021.02.03.12.45.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Feb 2021 12:45:12 -0800 (PST) Subject: Re: [PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210203165233.22177-1-jbx6244@gmail.com> Message-ID: <597269b3-3fc4-85a1-fecd-7ee2816e228b@gmail.com> Date: Wed, 3 Feb 2021 21:45:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20210203165233.22177-1-jbx6244@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Hi Rob, Heiko, Version 2 without node wrapper. Is that OK for backwards compatibility? New SoC rk3568 and rk3566 in the manufacturer tree also seem to use dwc3 usb, so now only a rk3399 node restyle in mainline with conversion to yaml. On 2/3/21 5:52 PM, Johan Jonker wrote: > In the past Rockchip dwc3 usb nodes were manually checked. > With the conversion of snps,dwc3.yaml as common document > we now can convert rockchip,dwc3.txt to yaml as well. > Remove node wrapper. > > Added properties for rk3399 are: > power-domains > resets > reset-names > > Signed-off-by: Johan Jonker > --- > .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ----------- > .../devicetree/bindings/usb/rockchip,dwc3.yaml | 103 +++++++++++++++++++++ > 2 files changed, 103 insertions(+), 56 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > deleted file mode 100644 > index 945204932..000000000 > --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > +++ /dev/null > @@ -1,56 +0,0 @@ > -Rockchip SuperSpeed DWC3 USB SoC controller > - > -Required properties: > -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC > -- clocks: A list of phandle + clock-specifier pairs for the > - clocks listed in clock-names > -- clock-names: Should contain the following: > - "ref_clk" Controller reference clk, have to be 24 MHz > - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz > - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS > - operation and >= 30MHz for HS operation > - "grf_clk" Controller grf clk > - > -Required child node: > -A child node must exist to represent the core DWC3 IP block. The name of > -the node is not important. The content of the node is defined in dwc3.txt. > - > -Phy documentation is provided in the following places: > -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY > -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY > - > -Example device nodes: > - > - usbdrd3_0: usb@fe800000 { > - compatible = "rockchip,rk3399-dwc3"; > - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, > - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; > - clock-names = "ref_clk", "suspend_clk", > - "bus_clk", "grf_clk"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - usbdrd_dwc3_0: dwc3@fe800000 { > - compatible = "snps,dwc3"; > - reg = <0x0 0xfe800000 0x0 0x100000>; > - interrupts = ; > - dr_mode = "otg"; > - }; > - }; > - > - usbdrd3_1: usb@fe900000 { > - compatible = "rockchip,rk3399-dwc3"; > - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, > - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; > - clock-names = "ref_clk", "suspend_clk", > - "bus_clk", "grf_clk"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - usbdrd_dwc3_1: dwc3@fe900000 { > - compatible = "snps,dwc3"; > - reg = <0x0 0xfe900000 0x0 0x100000>; > - interrupts = ; > - dr_mode = "otg"; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml > new file mode 100644 > index 000000000..fdf9497bc > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SuperSpeed DWC3 USB SoC controller > + > +maintainers: > + - Heiko Stuebner > + > +description: > + The common content of the node is defined in snps,dwc3.yaml. > + > + Phy documentation is provided in the following places. > + > + USB2.0 PHY > + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml > + > + Type-C PHY > + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt wrong indentation: expected 2 but found 6 (indentation) yamllint ./Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml This warning doesn't seem to show up with the command below. make ARCH=arm64 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml > + > +allOf: > + - $ref: snps,dwc3.yaml# No warning is given here with dt_binding_check. >From patchwork log: Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml' ///// What's the correct format? - $ref: snps,dwc3.yaml# or - $ref: "snps,dwc3.yaml#" ///// This serie is for linux-next. What kernel version does patchwork work test with? https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210203165233.22177-1-jbx6244@gmail.com/ > + > +properties: > + compatible: > + items: > + - enum: > + - rockchip,rk3399-dwc3 > + - const: snps,dwc3 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: > + Controller reference clock, must to be 24 MHz > + - description: > + Controller suspend clock, must to be 24 MHz or 32 KHz > + - description: > + Master/Core clock, must to be >= 62.5 MHz for SS > + operation and >= 30MHz for HS operation > + - description: > + Controller aclk_usb3_rksoc_axi_perf clock > + - description: > + Controller aclk_usb3 clock > + - description: > + Controller grf clock > + > + clock-names: > + items: > + - const: ref_clk > + - const: suspend_clk > + - const: bus_clk > + - const: aclk_usb3_rksoc_axi_perf > + - const: aclk_usb3 > + - const: grf_clk > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: usb3-otg > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + #include > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + usbdrd3_0: usb@fe800000 { > + compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; > + reg = <0x0 0xfe800000 0x0 0x100000>; > + interrupts = ; > + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, > + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, > + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; > + clock-names = "ref_clk", "suspend_clk", > + "bus_clk", "aclk_usb3_rksoc_axi_perf", > + "aclk_usb3", "grf_clk"; > + dr_mode = "otg"; > + }; > + }; >