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x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3654c925-77c6-42ca-3e61-08d6e4de6636 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:AM5PR0402MB2898; x-ms-traffictypediagnostic: AM5PR0402MB2898: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-forefront-prvs: 00531FAC2C x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(39860400002)(396003)(376002)(136003)(199004)(189003)(11346002)(446003)(86362001)(76176011)(66946007)(66066001)(6436002)(486006)(102836004)(6246003)(76116006)(3846002)(71200400001)(229853002)(6116002)(6506007)(478600001)(6916009)(53546011)(14454004)(55016002)(71190400001)(81156014)(81166006)(7736002)(25786009)(476003)(5660300002)(256004)(14444005)(74316002)(4326008)(54906003)(68736007)(66476007)(64756008)(305945005)(73956011)(66556008)(186003)(53936002)(66446008)(26005)(7696005)(52536014)(8936002)(9686003)(2906002)(316002)(99286004)(8676002)(33656002);DIR:OUT;SFP:1101;SCL:1;SRVR:AM5PR0402MB2898;H:AM5PR0402MB2865.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: eR7rGfmlB+wLICgzsDZhUzZ+ofQsel5yBmAKjilxU4tC5FZ5e0yH7WbLK0mB0roadQ6sldOERXa7beSiP+DP2vtQmtWCBR/C9y1S6PGDbkuNX5eCW+s/cs/lc8DX89VGiAj9WOmmxNsj6ld90X4MYWEV3Wr1qOxGVctwlT6uHRvyoZyanFxg3wLgQ9u/DX/bc3LgknZ0u0aUCiF6SvtAsRn3XjEdTTmcngj2XdF9+Exp+4rjTq0fQ0/EtKAf5kv1NX7+KGt+2ybUQ2geIykISlCHVaj7kCqq89X+hRWmK5R5zsH118csZ9U/lUtWMb1yLDf1KfnYWQGh4UAOuNgra4a8WlcyxEHIaKC3FDLVjeURWl2Jswx2bgLCcDbrHHGnewM9VBA/PH1P1HJX9EDKJ9BcprJfh4H5wgKd/XacqcE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3654c925-77c6-42ca-3e61-08d6e4de6636 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 May 2019 09:08:36.7066 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ran.wang_1@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0402MB2898 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Hi Felipe, On Tuesday, May 28, 2019 18:20, Felipe Balbi wrote: >=20 > >> >> > /* Global Debug Queue/FIFO Space Available Register */ > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) > >> >> > @@ -859,6 +867,7 @@ struct dwc3_scratchpad_array { > >> >> > * 3 - Reserved > >> >> > * @imod_interval: set the interrupt moderation interval in 250n= s > >> >> > * increments or 0 to disable. > >> >> > + * @dma_coherent: set if enable dma-coherent. > >> >> > >> >> you're not enabling dma coherency, you're enabling cache snooping. > >> >> And this property should describe that. Also, keep in mind that > >> >> different devices may want different cache types for each of those > >> >> fields, so your property would have to be a lot more complex. Somet= hing > like: > >> >> > >> >> snps,cache-type =3D , , ... > >> >> > >> >> Then driver would have to parse this properly to setup GSBUSCFG0. > > > > According to the DesignWare Cores SuperSpeed USB 3.0 Controller > > Databook (v2.60a), it has described Type Bit Assignments for all suppor= ted > master bus type: > > AHB, AXI3, AXI4 and Native. I found the bit definition are different am= ong > them. > > So, for the example you gave above, feel a little bit confused. > > Did you mean: > > snps,cache-type =3D , > "cacheable">, , >=20 > yeah, something like that. I think DATA_RD should be a macro, right? So, where I can put its define? Create a dwc3.h in include/dt-bindings/usb/ ? Another question about this remain open is: DWC3 data book's Table 6-5 Cache Type Bit Assignments show that bits definition will differ per MBUS_TYPEs as below: ---------------------------------------------------------------- = =20 MBUS_TYPE| bit[3] |bit[2] |bit[1] |bit[0] = =20 ---------------------------------------------------------------- = =20 AHB |Cacheable |Bufferable |Privilegge |Data = =20 AXI3 |Write Allocate|Read Allocate|Cacheable |Bufferable = =20 AXI4 |Allocate Other|Allocate |Modifiable |Bufferable = =20 AXI4 |Other Allocate|Allocate |Modifiable |Bufferable = =20 Native |Same as AXI |Same as AXI |Same as AXI|Same as AXI = =20 ---------------------------------------------------------------- = =20 Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain= =20 signals, which have the same meaning: = =20 Bufferable =3D Posted = =20 Cacheable =3D Modifiable =3D Snoop (negation of No Snoop) =20 For Layerscape SoCs, MBUS_TYPE is AXI3. So I am not sure how to use snps,cache-type =3D , to cover all MBUS_TYPE? (you can notice that AHB and AXI3's cacheable are on different bit) Or I just need to handle AXI3 case? Regards, Ran