From: Pawel Laszczak <pawell@cadence.com>
To: Roger Quadros <rogerq@ti.com>,
"felipe.balbi@linux.intel.com" <felipe.balbi@linux.intel.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jbergsagel@ti.com" <jbergsagel@ti.com>,
"nsekhar@ti.com" <nsekhar@ti.com>, "nm@ti.com" <nm@ti.com>,
Suresh Punnoose <sureshp@cadence.com>,
Jayshri Dajiram Pawar <jpawar@cadence.com>,
Rahul Kumar <kurahul@cadence.com>,
Anil Joy Varughese <aniljoy@cadence.com>
Subject: RE: [PATCH v10 5/6] usb:cdns3 Add Cadence USB3 DRD Driver
Date: Wed, 14 Aug 2019 14:30:05 +0000 [thread overview]
Message-ID: <BYAPR07MB4709941410AE163EB0627C16DDAD0@BYAPR07MB4709.namprd07.prod.outlook.com> (raw)
In-Reply-To: <2c5ed505-6fee-1816-e5bb-59a9ed96fb70@ti.com>
Hi Roger,
>
>On 21/07/2019 21:32, Pawel Laszczak wrote:
>> This patch introduce new Cadence USBSS DRD driver to Linux kernel.
>>
>> The Cadence USBSS DRD Controller is a highly configurable IP Core which
>> can be instantiated as Dual-Role Device (DRD), Peripheral Only and
>> Host Only (XHCI)configurations.
>>
>> The current driver has been validated with FPGA platform. We have
>> support for PCIe bus, which is used on FPGA prototyping.
>>
>> The host side of USBSS-DRD controller is compliant with XHCI
>> specification, so it works with standard XHCI Linux driver.
>>
>> Signed-off-by: Pawel Laszczak <pawell@cadence.com>
>> ---
>> drivers/usb/Kconfig | 2 +
>> drivers/usb/Makefile | 2 +
>> drivers/usb/cdns3/Kconfig | 46 +
>> drivers/usb/cdns3/Makefile | 17 +
>> drivers/usb/cdns3/cdns3-pci-wrap.c | 203 +++
>> drivers/usb/cdns3/core.c | 554 +++++++
>> drivers/usb/cdns3/core.h | 109 ++
>> drivers/usb/cdns3/debug.h | 171 ++
>> drivers/usb/cdns3/debugfs.c | 87 ++
>> drivers/usb/cdns3/drd.c | 390 +++++
>> drivers/usb/cdns3/drd.h | 166 ++
>> drivers/usb/cdns3/ep0.c | 914 +++++++++++
>> drivers/usb/cdns3/gadget-export.h | 28 +
>> drivers/usb/cdns3/gadget.c | 2338 ++++++++++++++++++++++++++++
>> drivers/usb/cdns3/gadget.h | 1321 ++++++++++++++++
>> drivers/usb/cdns3/host-export.h | 28 +
>> drivers/usb/cdns3/host.c | 71 +
>> drivers/usb/cdns3/trace.c | 11 +
>> drivers/usb/cdns3/trace.h | 493 ++++++
>> 19 files changed, 6951 insertions(+)
>> create mode 100644 drivers/usb/cdns3/Kconfig
>> create mode 100644 drivers/usb/cdns3/Makefile
>> create mode 100644 drivers/usb/cdns3/cdns3-pci-wrap.c
>> create mode 100644 drivers/usb/cdns3/core.c
>> create mode 100644 drivers/usb/cdns3/core.h
>> create mode 100644 drivers/usb/cdns3/debug.h
>> create mode 100644 drivers/usb/cdns3/debugfs.c
>> create mode 100644 drivers/usb/cdns3/drd.c
>> create mode 100644 drivers/usb/cdns3/drd.h
>> create mode 100644 drivers/usb/cdns3/ep0.c
>> create mode 100644 drivers/usb/cdns3/gadget-export.h
>> create mode 100644 drivers/usb/cdns3/gadget.c
>> create mode 100644 drivers/usb/cdns3/gadget.h
>> create mode 100644 drivers/usb/cdns3/host-export.h
>> create mode 100644 drivers/usb/cdns3/host.c
>> create mode 100644 drivers/usb/cdns3/trace.c
>> create mode 100644 drivers/usb/cdns3/trace.h
>>
>
><snip>
>
>> diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
>> new file mode 100644
>> index 000000000000..291f08be56fe
>> --- /dev/null
>> +++ b/drivers/usb/cdns3/gadget.c
>> @@ -0,0 +1,2338 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Cadence USBSS DRD Driver - gadget side.
>> + *
>> + * Copyright (C) 2018-2019 Cadence Design Systems.
>> + * Copyright (C) 2017-2018 NXP
>> + *
>> + * Authors: Pawel Jez <pjez@cadence.com>,
>> + * Pawel Laszczak <pawell@cadence.com>
>> + * Peter Chen <peter.chen@nxp.com>
>> + */
>> +
>
><snip>
>
>> +
>> +static void cdns3_gadget_config(struct cdns3_device *priv_dev)
>> +{
>> + struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
>> + u32 reg;
>> +
>> + cdns3_ep0_config(priv_dev);
>> +
>> + /* enable interrupts for endpoint 0 (in and out) */
>> + writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, ®s->ep_ien);
>> +
>> + /*
>> + * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
>> + * revision of controller.
>> + */
>> + if (priv_dev->dev_ver == DEV_VER_TI_V1) {
>> + reg = readl(®s->dbg_link1);
>> +
>> + reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
>> + reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
>> + DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
>> + writel(reg, ®s->dbg_link1);
>> + }
>> +
>> + /*
>> + * By default some platforms has set protected access to memory.
>> + * This cause problem with cache, so driver restore non-secure
>> + * access to memory.
>> + */
>> + reg = readl(®s->dma_axi_ctrl);
>
>Why read the reg at all if you are just overwriting it below?
>
>> + reg = DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
>> + DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
>
>
>Otherwise you need to read modify only necessary bits and then write.
Yes, we also has found this bug.
It's will be corrected in next version.
>i.e.
> #define DMA_AXI_CTRL_MAPROT_MASK 0x3
> reg &= ~(DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_MAPROT_MASK) |
> DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_MAPROT_MASK))
> reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
> DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
>
>> + writel(reg, ®s->dma_axi_ctrl);
>> +
>> + /* enable generic interrupt*/
>> + writel(USB_IEN_INIT, ®s->usb_ien);
>> + writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf);
>> +
>> + cdns3_configure_dmult(priv_dev, NULL);
>> +
>> + cdns3_gadget_pullup(&priv_dev->gadget, 1);
>> +}
>> +
>
><snip>
>
Cheers,
Pawell
next prev parent reply other threads:[~2019-08-14 14:30 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-21 18:32 [PATCH v10 0/6] Introduced new Cadence USBSS DRD Driver Pawel Laszczak
2019-07-21 18:32 ` [PATCH v10 1/6] dt-bindings: add binding for USBSS-DRD controller Pawel Laszczak
2019-07-21 18:32 ` [PATCH v10 2/6] usb:common Separated decoding functions from dwc3 driver Pawel Laszczak
2019-07-21 19:05 ` Joe Perches
2019-07-21 20:45 ` Alan Stern
2019-07-21 20:54 ` Joe Perches
2019-07-22 10:06 ` Pawel Laszczak
2019-07-22 11:49 ` gregkh
2019-07-21 18:32 ` [PATCH v10 3/6] usb:common Patch simplify usb_decode_set_clear_feature function Pawel Laszczak
2019-07-21 19:07 ` Joe Perches
2019-07-22 10:12 ` Pawel Laszczak
2019-07-21 18:32 ` [PATCH v10 4/6] usb:common Simplify usb_decode_get_set_descriptor function Pawel Laszczak
2019-07-21 18:32 ` [PATCH v10 5/6] usb:cdns3 Add Cadence USB3 DRD Driver Pawel Laszczak
2019-07-31 3:36 ` Pawel Laszczak
2019-08-07 12:08 ` Roger Quadros
2019-08-11 11:59 ` Pawel Laszczak
2019-08-12 8:45 ` Roger Quadros
2019-08-12 9:43 ` Pawel Laszczak
2019-08-12 10:31 ` Heikki Krogerus
2019-08-12 11:05 ` Roger Quadros
2019-08-12 12:46 ` Felipe Balbi
2019-08-12 13:04 ` Roger Quadros
2019-08-13 5:15 ` Felipe Balbi
2019-08-13 7:30 ` Chunfeng Yun
2019-08-13 7:48 ` Roger Quadros
2019-08-13 8:50 ` Chunfeng Yun
2019-08-12 10:05 ` Roger Quadros
2019-08-12 11:10 ` Pawel Laszczak
2019-08-14 13:32 ` Roger Quadros
2019-08-15 6:10 ` Felipe Balbi
2019-08-19 8:20 ` Pawel Laszczak
2019-08-14 13:38 ` Roger Quadros
2019-08-14 14:30 ` Pawel Laszczak [this message]
2019-08-15 11:22 ` Roger Quadros
2019-08-19 10:30 ` Pawel Laszczak
2019-08-19 10:59 ` Roger Quadros
2019-08-23 8:53 ` Vignesh Raghavendra
2019-08-23 9:39 ` Pawel Laszczak
2019-08-26 2:16 ` Peter Chen
2019-08-26 7:53 ` Pawel Laszczak
2019-07-21 18:32 ` [PATCH v10 6/6] usb:cdns3 Fix for stuck packets in on-chip OUT buffer Pawel Laszczak
2019-07-21 19:03 ` [PATCH v10 0/6] Introduced new Cadence USBSS DRD Driver Pavel Machek
2019-07-22 9:58 ` Pawel Laszczak
2019-07-22 11:48 ` gregkh
2019-07-22 11:56 ` Pavel Machek
2019-07-22 12:11 ` gregkh
2019-07-22 12:11 ` Pawel Laszczak
2019-07-22 21:00 ` Pavel Machek
2019-07-23 4:32 ` Pawel Laszczak
2019-08-07 11:05 ` Roger Quadros
2019-08-08 4:12 ` Pawel Laszczak
2019-08-09 10:36 ` Roger Quadros
2019-08-09 10:44 ` Felipe Balbi
2019-08-13 8:22 ` Pavel Machek
2019-08-15 12:12 ` Roger Quadros
2019-08-15 14:39 ` Alan Stern
2019-08-19 12:08 ` Roger Quadros
2019-08-19 14:19 ` Alan Stern
2019-08-21 9:54 ` Roger Quadros
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