Re: [PATCH v3 1/5] dt-bindings: usb: convert ti,hd3ss3220 bindings to json-schema

[Rob Herring <robh@kernel.org>]

On Wed, Sep 9, 2020 at 2:21 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v3 1/5] dt-bindings: usb: convert ti,hd3ss3220 bindings to
> > json-schema
> >
> > On Mon, Aug 24, 2020 at 03:10:49PM +0100, Biju Das wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Convert ti,hd3ss3220.txt to YAML. Updated the binding documentation as
> > > graph bindings of this device model Super Speed (SS) data bus to the
> > > Super Speed (SS) capable connector.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-
> > lad.rj@bp.renesas.com>
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v2->v3: Replaced Tabs with spaces in the example section.
> > > v1->v2 : No change
> > > Ref: https://patchwork.kernel.org/patch/11669423/
> > > ---
> > >  .../devicetree/bindings/usb/ti,hd3ss3220.txt  | 38 ---------
> > > .../devicetree/bindings/usb/ti,hd3ss3220.yaml | 81
> > +++++++++++++++++++
> > >  2 files changed, 81 insertions(+), 38 deletions(-)  delete mode
> > > 100644 Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
> > >  create mode 100644
> > > Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
> > > b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
> > > deleted file mode 100644
> > > index 2bd21b22ce95..000000000000
> > > --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
> > > +++ /dev/null
> > > @@ -1,38 +0,0 @@
> > > -TI HD3SS3220 TypeC DRP Port Controller.
> > > -
> > > -Required properties:
> > > - - compatible: Must be "ti,hd3ss3220".
> > > - - reg: I2C slave address, must be 0x47 or 0x67 based on ADDR pin.
> > > - - interrupts: An interrupt specifier.
> > > -
> > > -Required sub-node:
> > > - - connector: The "usb-c-connector" attached to the hd3ss3220 chip. The
> > > -   bindings of the connector node are specified in:
> > > -
> > > -Documentation/devicetree/bindings/connector/usb-connector.yaml
> > > -
> > > -Example:
> > > -hd3ss3220@47 {
> > > -compatible = "ti,hd3ss3220";
> > > -reg = <0x47>;
> > > -interrupt-parent = <&gpio6>;
> > > -interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > > -
> > > -connector {
> > > -compatible = "usb-c-connector";
> > > -label = "USB-C";
> > > -data-role = "dual";
> > > -
> > > -ports {
> > > -#address-cells = <1>;
> > > -#size-cells = <0>;
> > > -
> > > -port@1 {
> > > -reg = <1>;
> > > -hd3ss3220_ep: endpoint {
> > > -remote-endpoint =
> > <&usb3_role_switch>;
> > > -};
> > > -};
> > > -};
> > > -};
> > > -};
> > > diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml
> > > b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml
> > > new file mode 100644
> > > index 000000000000..750a099529c0
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml
> > > @@ -0,0 +1,81 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: TI HD3SS3220 TypeC DRP Port Controller
> > > +
> > > +maintainers:
> > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description: |-
> > > +  HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port
> > > +controller. The device provides Channel
> > > +  Configuration (CC) logic and 5V VCONN sourcing for ecosystems
> > > +implementing USB Type-C. The
> > > +  HD3SS3220 can be configured as a Downstream Facing Port (DFP),
> > > +Upstream Facing Port (UFP) or a
> > > +  Dual Role Port (DRP) making it ideal for any application.
> > > +
> > > +properties:
> > > +  compatible:
> > > +   const: ti,hd3ss3220
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  interrupts:
> > > +    maxItems: 1
> > > +
> > > +  ports:
> > > +    description: OF graph bindings (specified in bindings/graph.txt) that
> > model
> > > +      SS data bus to the SS capable connector.
> > > +    type: object
> > > +    properties:
> > > +      port@0:
> > > +        type: object
> > > +        description: Super Speed (SS) capable connector.
> > > +
> > > +      port@1:
> > > +        type: object
> > > +        description: Super Speed (SS) data bus.
> > > +
> > > +    required:
> > > +      - port@0
> > > +      - port@1
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - interrupts
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    i2c0 {
> > > +        #address-cells = <1>;
> > > +        #size-cells = <0>;
> > > +
> > > +        hd3ss3220@47 {
> > > +                compatible = "ti,hd3ss3220";
> > > +                reg = <0x47>;
> > > +                interrupt-parent = <&gpio6>;
> > > +                interrupts = <3>;
> > > +
> > > +                ports {
> > > +                        #address-cells = <1>;
> > > +                        #size-cells = <0>;
> > > +                        port@0 {
> > > +                                reg = <0>;
> > > +                                hd3ss3220_in_ep: endpoint {
> > > +                                        remote-endpoint = <&ss_ep>;
> > > +                                };
> > > +                        };
> > > +                        port@1 {
> > > +                                reg = <1>;
> > > +                                hd3ss3220_out_ep: endpoint {
> > > +                                        remote-endpoint = <&usb3_role_switch>;
> > > +                                };
> >
> > If you have 2 inputs muxed, then there would be 2 endpoints here? Please
> > show the fullest or most complicated case for the example. The port@1
> > description could be a bit better.
>
> As per [1] "HD3SS3220 has integrated USB 3.0/3.1 SS/SS+ MUX with 2 channel 2:1 switching required to handle cable flips".
> The four Superspeed differential pairs (two Tx and two Rx pairs) pairs from the USB-C receptacle is connected to this device
> and the output of the Mux is connected to the  SoC .

Ah, I was thinking this was muxing 2 functions (such as DP) rather
than cable flip handling. I guess the example doesn't need anything
else, but the description does. In the case of directly connected to
the SoC, how are cable flips handled? The SoC phy handles it?

There's some issues in the connector binding with how the SS signals
are handled that needs to be solved. This all needs to be addressed
looking at various possible h/w designs.

Rob