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From: Rob Herring <robh@kernel.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: JC Kuo <jckuo@nvidia.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jon Hunter <jonathanh@nvidia.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	linux-tegra@vger.kernel.org,
	Linux USB List <linux-usb@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org,
	Nagarjuna Kristam <nkristam@nvidia.com>
Subject: Re: [PATCH v4 3/5] dt-bindings: phy: tegra: Add Tegra194 support
Date: Mon, 14 Oct 2019 08:40:37 -0500
Message-ID: <CAL_Jsq+aKxfAir3skanfqmM+nFFzXPFL4eMa-+pq1kH-90YTbg@mail.gmail.com> (raw)
In-Reply-To: <20191014131752.GF422231@ulmo>

On Mon, Oct 14, 2019 at 8:17 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Herring wrote:
> > On Wed, Oct 09, 2019 at 10:43:41AM +0800, JC Kuo wrote:
> > > Extend the bindings to cover the set of features found in Tegra194.
> > > Note that, technically, there are four more supplies connected to the
> > > XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
> > > , but the power sequencing requirements of Tegra194 require these to be
> > > under the control of the PMIC.
> > >
> > > Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is
> > > possible for some platforms have long signal trace that could not
> > > provide sufficient electrical environment for Gen 2 speed. To deal with
> > > this, a new device node property "nvidia,disable-gen2" was added to
> > > Tegra194 that be used to specifically disable Gen 2 speed for a
> > > particular USB 3.0 port so that the port can be limited to Gen 1 speed
> > > and avoid the instability.
> >
> > I suspect this may be a common issue and we should have a common
> > property. Typically, this kind of property is in the controller though
> > and supports multiple speed limits. See PCI bindings for inspiration.
>
> Given that support for gen 2 speeds is dependent on signal trace length,
> it doesn't really make sense to restrict the whole controller to a given
> speed if only the signal trace for a single port exceeds the limit for
> which gen 2 would work.
>
> Also, the USB PHYs are in a different hardware block than the USB
> controller, so this really is a property of the PHY block, not the USB
> controller.

Okay, but still should be common for USB PHYs IMO.

Rob

  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-09  2:43 [PATCH v4 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
2019-10-09  2:43 ` [PATCH v4 1/5] phy: tegra: xusb: Protect Tegra186 soc with config JC Kuo
2019-10-14 13:11   ` Thierry Reding
2019-10-09  2:43 ` [PATCH v4 2/5] phy: tegra: xusb: Add Tegra194 support JC Kuo
2019-10-14 13:12   ` Thierry Reding
2019-10-09  2:43 ` [PATCH v4 3/5] dt-bindings: phy: tegra: " JC Kuo
2019-10-09 23:39   ` Rob Herring
2019-10-14 13:17     ` Thierry Reding
2019-10-14 13:40       ` Rob Herring [this message]
2019-10-17  7:48         ` JC Kuo
2019-10-17 11:44           ` Thierry Reding
2019-10-17 12:01           ` Thierry Reding
2019-10-09  2:43 ` [PATCH v4 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194 JC Kuo
2019-10-09  2:43 ` [PATCH v4 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board JC Kuo

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