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From: Peter Geis <pgwipeout@gmail.com>
To: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: katsuhiro@katsuster.net, linux-rockchip@lists.infradead.org,
	linux-usb@vger.kernel.org, Robin Murphy <robin.murphy@arm.com>,
	Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH 4/5] arm64: dts: rockchip: add usb3 to rk3328 devicetree
Date: Wed, 30 Oct 2019 13:54:32 -0400	[thread overview]
Message-ID: <CAMdYzYoKe5VSRb7Yf9C50YAkBSgvLB+5U15b_ndxaSFxUfGVQQ@mail.gmail.com> (raw)
In-Reply-To: <1572402485.18464.22.camel@mhfsdcap03>

On Tue, Oct 29, 2019 at 10:28 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
>
> On Tue, 2019-10-29 at 11:31 -0400, Peter Geis wrote:
> > On Mon, Oct 28, 2019 at 9:59 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> > >
> > > On Mon, 2019-10-28 at 18:22 +0000, Peter Geis wrote:
> > > > Now that we have a proper phy driver, we can add the requisite bits to the
> > > > rk3328 device tree.
> > > > Added the u3drd and u3phy nodes.
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > > ---
> > > >  arch/arm64/boot/dts/rockchip/rk3328.dtsi | 72 ++++++++++++++++++++++++
> > > >  1 file changed, 72 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> > > > index 31cc1541f1f5..072e988ad655 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> > > > @@ -805,6 +805,47 @@
> > > >               };
> > > >       };
> > > >
> > > > +     usb3phy_grf: syscon@ff460000 {
> > > > +             compatible = "rockchip,usb3phy-grf", "syscon";
> > > > +             reg = <0x0 0xff460000 0x0 0x1000>;
> > > > +     };
> > > > +
> > > > +     u3phy: usb3-phy@ff470000 {
> > > usb-phy?
> >
> > This change does not seem wise, as there are also various usb2-phys
> > that are controlled via other drivers, while the usb3phy also has to
> > support usb2 as a fallback.
> We can use u3phy label, or phy-cells = <1>, to provide phys type to
> distighuish u3/u2phy if need.
>
> >
> > > > +             compatible = "rockchip,rk3328-u3phy";
> > > > +             reg = <0x0 0xff470000 0x0 0x0>;
> > > It's zero length, may be not necessary, how about use ranges with
> > > parameter ?
> >
> > I'll look into this.
> >
> > >
> > > > +             rockchip,u3phygrf = <&usb3phy_grf>;
> > > > +             rockchip,grf = <&grf>;
> > > > +             interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> > > > +             interrupt-names = "linestate";
> > > > +             clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
> > > > +             clock-names = "u3phy-otg", "u3phy-pipe";
> > > To me, no need u3phy prefix
> >
> > Same as above, since this could cause confusion with the usb2 phy devices.
> Other info can be used, e.g. compatible;
>
>
> >
> > > > +             resets = <&cru SRST_USB3PHY_U2>,
> > > > +                      <&cru SRST_USB3PHY_U3>,
> > > > +                      <&cru SRST_USB3PHY_PIPE>,
> > > > +                      <&cru SRST_USB3OTG_UTMI>,
> > > > +                      <&cru SRST_USB3PHY_OTG_P>,
> > > > +                      <&cru SRST_USB3PHY_PIPE_P>;
> > > > +             reset-names = "u3phy-u2-por", "u3phy-u3-por",
> > > > +                           "u3phy-pipe-mac", "u3phy-utmi-mac",
> > > > +                           "u3phy-utmi-apb", "u3phy-pipe-apb";
> > > ditto
> > >
> > > > +             #address-cells = <2>;
> > > > +             #size-cells = <2>;
> > > > +             ranges;
> > > > +             status = "disabled";
> > > > +
> > > > +             u3phy_utmi: utmi@ff470000 {
> > > usb-phy instead of utmi?
> >
> > The stock driver looks for these by name, and they are both different functions.
> > This change would break the driver.
> Use phy_type? refer to bindings/usb/generic.txt

Roger, thank you for your feedback.
I have a bit of work to do for v2, although I'm hoping for a few more
tests to come in.
So far all I have is my rk3328-roc-cc and Robin's test.

>
> >
> > >
> > > > +                     reg = <0x0 0xff470000 0x0 0x8000>;
> > > > +                     #phy-cells = <0>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > > +             u3phy_pipe: pipe@ff478000 {
> > > usb-phy
> >
> > Same as above.
> >
> > > > +                     reg = <0x0 0xff478000 0x0 0x8000>;
> > > > +                     #phy-cells = <0>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +     };
> > > > +
> > > >       sdmmc: dwmmc@ff500000 {
> > > >               compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
> > > >               reg = <0x0 0xff500000 0x0 0x4000>;
> > > > @@ -936,6 +977,37 @@
> > > >               status = "disabled";
> > > >       };
> > > >
> > > > +     usbdrd3: usb@ff600000 {
> > > > +             compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
> > > > +             clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
> > > > +                      <&cru SCLK_USB3OTG_SUSPEND>;
> > > > +             clock-names = "ref", "bus_early",
> > > > +                           "suspend";
> > > > +             #address-cells = <2>;
> > > > +             #size-cells = <2>;
> > > > +             ranges;
> > > > +             clock-ranges;
> > > > +             status = "disabled";
> > > > +
> > > > +             usbdrd_dwc3: dwc3@ff600000 {
> > > > +                     compatible = "snps,dwc3";
> > > > +                     reg = <0x0 0xff600000 0x0 0x100000>;
> > > > +                     interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> > > > +                     dr_mode = "otg";
> > > > +                     phys = <&u3phy_utmi>, <&u3phy_pipe>;
> > > > +                     phy-names = "usb2-phy", "usb3-phy";
> > > > +                     phy_type = "utmi_wide";
> > > > +                     snps,dis_enblslpm_quirk;
> > > > +                     snps,dis-u2-freeclk-exists-quirk;
> > > > +                     snps,dis_u2_susphy_quirk;
> > > > +                     snps,dis_u3_susphy_quirk;
> > > > +                     snps,dis-del-phy-power-chg-quirk;
> > > > +                     snps,dis-tx-ipgap-linecheck-quirk;
> > > > +                     snps,xhci-trb-ent-quirk;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +     };
> > > > +
> > > >       gic: interrupt-controller@ff811000 {
> > > >               compatible = "arm,gic-400";
> > > >               #interrupt-cells = <3>;
> > >
> > >
> > >
> > > _______________________________________________
> > > Linux-rockchip mailing list
> > > Linux-rockchip@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>

  reply	other threads:[~2019-10-30 17:54 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 18:22 [PATCH 0/5] add rk3328 usb3 phy driver Peter Geis
2019-10-28 18:22 ` [PATCH 1/5] phy: rockchip: add inno-usb3 " Peter Geis
2019-10-29  2:11   ` Chunfeng Yun
2019-10-29 15:26     ` Peter Geis
2019-10-30  2:59       ` Chunfeng Yun
2019-10-30 17:50         ` Peter Geis
2019-10-30  8:15   ` Heiko Stuebner
2019-10-30 17:46     ` Peter Geis
2019-10-31 14:02       ` Peter Geis
2019-10-28 18:22 ` [PATCH 2/5] dt-bindings: clean up rockchip grf binding document Peter Geis
2019-10-31 14:25   ` Heiko Stuebner
2019-10-28 18:22 ` [PATCH 3/5] Documentation: bindings: add dt documentation for rockchip usb3 phy Peter Geis
2019-10-28 18:22 ` [PATCH 4/5] arm64: dts: rockchip: add usb3 to rk3328 devicetree Peter Geis
2019-10-29  1:58   ` Chunfeng Yun
2019-10-29 15:31     ` Peter Geis
2019-10-30  2:28       ` Chunfeng Yun
2019-10-30 17:54         ` Peter Geis [this message]
2019-10-28 18:22 ` [PATCH 5/5] arm64: dts: rockchip: enable usb3 on rk3328-roc-cc Peter Geis
2019-10-28 18:41 ` [PATCH 0/5] add rk3328 usb3 phy driver Robin Murphy
2019-10-30  0:17   ` Robin Murphy
2019-10-30  1:15     ` Peter Geis
2020-04-23 20:20       ` Peter Geis

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