Re: [RFT][PATCH] usb: dwc3: Decouple USB 2.0 L1 & L2 events

[Amit Pundir <amit.pundir@linaro.org>]

On Wed, 18 Aug 2021 at 06:59, Jack Pham <jackp@codeaurora.org> wrote:
>
> On Thu, Aug 12, 2021 at 01:26:35AM -0700, Jack Pham wrote:
> > On DWC_usb3 revisions 3.00a and newer (including DWC_usb31 and
> > DWC_usb32) the GUCTL1 register gained the DEV_DECOUPLE_L1L2_EVT
> > field (bit 31) which when enabled allows the controller in device
> > mode to treat USB 2.0 L1 LPM & L2 events separately.
> >
> > After commit d1d90dd27254 ("usb: dwc3: gadget: Enable suspend
> > events") the controller will now receive events (and therefore
> > interrupts) for every state change when entering/exiting either
> > L1 or L2 states.  Since L1 is handled entirely by the hardware
> > and requires no software intervention, there is no need to even
> > enable these events and unnecessarily notify the gadget driver.
> > Enable the aforementioned bit to help reduce the overall interrupt
> > count for these L1 events that don't need to be handled while
> > retaining the events for full L2 suspend/wakeup.
>
> Hi folks in To:
>
> I'd like to request if any of you could help test this patch on your
> boards to help make sure it doesn't cause any regressions since I know
> some of the recent dwc3 patches from Qualcomm have been found to break
> other devices :(. So I'm hoping to avoid that even for a patch as
> small as this.
>
> Hoping this could be tried out on boards/SoCs such as db845c, hikey960,
> Exynos, the Intel "lakes", etc.  Ideally this needs validation with a
> high-speed connection to a USB 3.x host, which increases the chances
> that USB 2.0 Link Power Management is supported.
>
> The overall goal of this patch is to eliminate events generated for
> L1 entry/exit, so we should see a slight reduction in interrupt counts
> when checking `grep dwc3 /proc/interrupts` for comparable traffic.
>
> Appreciate any feedback and help in testing!

Smoke tested this patch on RB5, running android-mainline (v5.14-rc6)
kernel, with a USB 3.x host.
Pushed/Pulled couple of large files over ADB, hotplugged the cable a
few times and found no obvious regressions.

Tested-by: Amit Pundir <amit.pundir@linaro.org> # for RB5 (sm8250)

Regards,
Amit Pundir

> Thanks,
> Jack
>
> > Signed-off-by: Jack Pham <jackp@codeaurora.org>
> > ---
> >  drivers/usb/dwc3/core.c | 9 +++++++++
> >  drivers/usb/dwc3/core.h | 5 +++--
> >  2 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index ba74ad7f6995..719dac228703 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1050,6 +1050,15 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >               if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
> >                       reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
> >
> > +             /*
> > +              * Decouple USB 2.0 L1 & L2 events which will allow for
> > +              * gadget driver to only receive U3/L2 suspend & wakeup
> > +              * events and prevent the more frequent L1 LPM transitions
> > +              * from interrupting the driver.
> > +              */
> > +             if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
> > +                     reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
> > +
> >               if (dwc->dis_tx_ipgap_linecheck_quirk)
> >                       reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index 5991766239ba..356b94a7ec70 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -256,9 +256,10 @@
> >  #define DWC3_GUCTL_HSTINAUTORETRY    BIT(14)
> >
> >  /* Global User Control 1 Register */
> > -#define DWC3_GUCTL1_PARKMODE_DISABLE_SS      BIT(17)
> > +#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT    BIT(31)
> >  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS   BIT(28)
> > -#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW        BIT(24)
> > +#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW                BIT(24)
> > +#define DWC3_GUCTL1_PARKMODE_DISABLE_SS              BIT(17)
> >
> >  /* Global Status Register */
> >  #define DWC3_GSTS_OTG_IP     BIT(10)
> > --
> > 2.24.0
> >
>
> --
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