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Tue, 9 Jul 2019 03:55:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=l7JOqoZNLF1ch2AXaETC6HGqHaRuhuy6+juS3/DgGdc=; b=XhtqQP9aiQyyWmUlJ2fsn6lQ9DnHBOi9cR0RE8+Ur4APKHlRTp4wQrmsXq+pqUslTWWmWwKmKpvzRSnjUMha01K+66Wixt0NejRapsc9M8iTwJvdRQ0XHPXhJ/iscCK8OUA846b6M/Jt+js67ZvZalaNhjZySGaGmk+k6Ge6y74= Received: from VE1PR04MB6655.eurprd04.prod.outlook.com (20.179.235.94) by VE1PR04MB6735.eurprd04.prod.outlook.com (20.179.235.212) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2052.19; Tue, 9 Jul 2019 07:55:31 +0000 Received: from VE1PR04MB6655.eurprd04.prod.outlook.com ([fe80::846e:134d:2731:fcd]) by VE1PR04MB6655.eurprd04.prod.outlook.com ([fe80::846e:134d:2731:fcd%7]) with mapi id 15.20.2052.020; Tue, 9 Jul 2019 07:55:31 +0000 From: Ran Wang To: Felipe Balbi , Rob Herring CC: Greg Kroah-Hartman , "open list:DESIGNWARE USB3 DRD IP DRIVER" , open list , Rob Herring , "devicetree@vger.kernel.org" , Leo Li Subject: RE: [PATCH] usb: dwc3: Enable the USB snooping Thread-Topic: [PATCH] usb: dwc3: Enable the USB snooping Thread-Index: AQHTXdpMV/QBUrO8J0eNmcCmR0ATg6MVIlkAgAAD6zCAABVWgINueaJwgAAMz4CAAwpoAIAF38DwgBavPgCACkIu0IAASk0AgBejzDA= Date: Tue, 9 Jul 2019 07:55:30 +0000 Message-ID: References: <20171115060459.45375-1-ran.wang_1@nxp.com> <87ineb9b5v.fsf@linux.intel.com> <87shdfet90.fsf@linux.intel.com> <87k1eaanjw.fsf@linux.intel.com> <87o92wgyqj.fsf@linux.intel.com> <87v9wvsex3.fsf@linux.intel.com> In-Reply-To: <87v9wvsex3.fsf@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=ran.wang_1@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /LBlbvyE4InEq3vOIdp05vwA/+sTkagOMRYEP8wQNKiN0N8MN6MBVh0DM2P2AJ+Me5NKpXA7HLzfc3/a0HCjuErNQiYpz/mf4TW3UCLOsrRzd41lctK+GvJu+KattMuWG+mPbXs8jrCUseoi/g/S3f66jc1VBLoDVmjnN2NsESakVXl8w+ZgQOqt8XlMdXILEFVGwvYNRKU0neyjOLCztSr8bBxgw1Oa2kpSDzFZMf3WK9O9FsW5KayQJeSTTKYTT62TPPXzVFvO0OEYRZMrViVbJ9CWD+ANSmTeE4cIRnH22H68/3Ae9ueaFxRNO+12o9LJztw/SrrglINeKz7cEgmel7U4VrUsDVoJOdoV5PNvCfo5OiayI878z0COKmw+ySduzWQngKuZnghEr9celEtSepvQpORfMdZg8CBb5SE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9c4a4c7-3feb-476e-7082-08d70442d097 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2019 07:55:30.8443 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ran.wang_1@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6735 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Hi Felipe, On Monday, June 24, 2019 13:58, Felipe Balbi wrote: >=20 > Hi, >=20 > Ran Wang writes: > >> >> > >> >> > /* Global Debug Queue/FIFO Space Available Register */ > >> >> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) > >> >> > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) > >> >> > >> >> > @@ -859,6 +867,7 @@ struct dwc3_scratchpad_array { > >> >> > >> >> > * 3 - Reserved > >> >> > >> >> > * @imod_interval: set the interrupt moderation interval= in > 250ns > >> >> > >> >> > * increments or 0 to disable. > >> >> > >> >> > + * @dma_coherent: set if enable dma-coherent. > >> >> > >> >> > >> >> > >> >> you're not enabling dma coherency, you're enabling cache > snooping. > >> >> > >> >> And this property should describe that. Also, keep in mind > >> >> > >> >> that different devices may want different cache types for > >> >> > >> >> each of those fields, so your property would have to be a > >> >> > >> >> lot more complex. Something > >> >> > like: > >> >> > >> >> > >> >> > >> >> snps,cache-type =3D , , ... > >> >> > >> >> > >> >> > >> >> Then driver would have to parse this properly to setup GSBU= SCFG0. > >> >> > > > >> >> > > According to the DesignWare Cores SuperSpeed USB 3.0 > >> >> > > Controller Databook (v2.60a), it has described Type Bit > >> >> > > Assignments for all supported > >> >> > master bus type: > >> >> > > AHB, AXI3, AXI4 and Native. I found the bit definition are > >> >> > > different among > >> >> > them. > >> >> > > So, for the example you gave above, feel a little bit confused. > >> >> > > Did you mean: > >> >> > > snps,cache-type =3D , >> >> > > "cacheable">, , >> >> > > allocate"> > >> >> > > >> >> > yeah, something like that. > >> >> > >> >> I think DATA_RD should be a macro, right? So, where I can put its = define? > >> >> Create a dwc3.h in include/dt-bindings/usb/ ? > >> > > >> > Could you please give me some advice here? I'd like to prepare next > >> > version patch after getting this settled. > >> > > >> >> Another question about this remain open is: DWC3 data book's Table > >> >> 6-5 Cache Type Bit Assignments show that bits definition will > >> >> differ per MBUS_TYPEs as > >> >> below: > >> >> ---------------------------------------------------------------- > >> >> MBUS_TYPE| bit[3] |bit[2] |bit[1] |bit[0] > >> >> ---------------------------------------------------------------- > >> >> AHB |Cacheable |Bufferable |Privilegge |Data > >> >> AXI3 |Write Allocate|Read Allocate|Cacheable |Bufferable > >> >> AXI4 |Allocate Other|Allocate |Modifiable |Bufferable > >> >> AXI4 |Other Allocate|Allocate |Modifiable |Bufferable > >> >> Native |Same as AXI |Same as AXI |Same as AXI|Same as AXI > >> >> ---------------------------------------------------------------- > >> >> Note: The AHB, AXI3, AXI4, and PCIe busses use different names > >> >> for certain signals, which have the same meaning: > >> >> Bufferable =3D Posted > >> >> Cacheable =3D Modifiable =3D Snoop (negation of No Snoop) > >> >> > >> >> For Layerscape SoCs, MBUS_TYPE is AXI3. So I am not sure how to > >> >> use snps,cache-type =3D , to cover all > MBUS_TYPE? > >> >> (you can notice that AHB and AXI3's cacheable are on different > >> >> bit) Or I just need to handle AXI3 case? > >> > > >> > Also on this open. Thank you in advance. > >> > >> You could pass two strings and let the driver process them. Something > >> like: > >> > >> snps,cache_type =3D <"data_wr" "write allocate">, <"desc_rd" > >> "cacheable">... > >> > >> And so on. The only thing missing is for the mbus_type to be known by = the > driver. > >> Is that something we can figure out on any of the HWPARAMS registers > >> or does it have to be told explicitly? > > > > I have checked Layerscape Reference manual, HWPARAMS0~8 doesn't > > contain mbus_type Info, and I didn't know where have declared it explic= itly. > > > >> Another option would be to pass a string followed by one hex digit for= the > bits: > >> > >> snps,cache_type =3D <"data_wr" 0x8>, <"desc_rd" 0x2>...; > >> > >> Then we don't need to describe mbus_type since the bits are what matte= rs. For this option, looks like DTC doesn't allow form of <"data_wr" 0x8>, <"de= sc_rd" 0x2>...=20 It will report error when compiling: DTC arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dtb Error: arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi:383.23-24 syntax erro= r FATAL ERROR: Unable to parse input tree scripts/Makefile.lib:294: recipe for target 'arch/arm64/boot/dts/freescale/= fsl-ls1088a-qds.dtb' failed make[2]: *** [arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... Error: arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi:383.23-24 syntax erro= r FATAL ERROR: Unable to parse input tree One of the solution I can figure out is to use macro to replace "data_wr", = like below: , ... However, it will require creating file in include/dt-bindings/usb/dwc3.h to place macro definitions. Or may I use: "data_wr", <0x8>, "desc_rd", <0x2>... ? Thanks & Regards, Ran > > Yes, it's also what we prefer to use, it will be more flexible, I can > > add above Table > > 6-5 Cache Type Bit Assignments in binding to help user decide which > > value they would use. > > > > I would submit another version of patch for further review, thank you v= ery > much. >=20 > cool, thanks >=20 > -- > balbi