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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id c21sm939260ooj.33.2021.06.22.20.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jun 2021 20:37:44 -0700 (PDT) Date: Tue, 22 Jun 2021 22:37:41 -0500 From: Bjorn Andersson To: Iskren Chernev Cc: Andy Gross , Greg Kroah-Hartman , Kishon Vijay Abraham I , Manu Gautam , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: Re: [PATCH v1 3/3] phy: qcom-qusb2: Add configuration for SM4250 and SM6115 Message-ID: References: <20210622203240.559979-1-iskren.chernev@gmail.com> <20210622203240.559979-4-iskren.chernev@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210622203240.559979-4-iskren.chernev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On Tue 22 Jun 15:32 CDT 2021, Iskren Chernev wrote: > The SM4250 and SM6115 uses the same register layout as MSM8996, but the > tune sequence is a bit different. > Didn't review the initialization sequence, but it's different from the existing ones so adding a new compatible and init_tbl seems to be the right choice. Reviewed-by: Bjorn Andersson Regards, Bjorn > Signed-off-by: Iskren Chernev > --- > drivers/phy/qualcomm/phy-qcom-qusb2.c | 34 +++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c > index 8f1bf7e2186b..3c1d3b71c825 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c > +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c > @@ -219,6 +219,22 @@ static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { > QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), > }; > > +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { > + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), > + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), > + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), > + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), > + > + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), > + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), > + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), > + > + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), > + > + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), > + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), > +}; > + > static const unsigned int qusb2_v2_regs_layout[] = { > [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, > [QUSB2PHY_PLL_STATUS] = 0x1a0, > @@ -342,6 +358,18 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = { > .autoresume_en = BIT(3), > }; > > +static const struct qusb2_phy_cfg sm6115_phy_cfg = { > + .tbl = sm6115_init_tbl, > + .tbl_num = ARRAY_SIZE(sm6115_init_tbl), > + .regs = msm8996_regs_layout, > + > + .has_pll_test = true, > + .se_clk_scheme_default = true, > + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), > + .mask_core_ready = PLL_LOCKED, > + .autoresume_en = BIT(3), > +}; > + > static const char * const qusb2_phy_vreg_names[] = { > "vdda-pll", "vdda-phy-dpdm", > }; > @@ -888,6 +916,12 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { > }, { > .compatible = "qcom,sdm660-qusb2-phy", > .data = &sdm660_phy_cfg, > + }, { > + .compatible = "qcom,sm4250-qusb2-phy", > + .data = &sm6115_phy_cfg, > + }, { > + .compatible = "qcom,sm6115-qusb2-phy", > + .data = &sm6115_phy_cfg, > }, { > /* > * Deprecated. Only here to support legacy device > -- > 2.31.1 >