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Subject: Re: [PATCH v3 00/15] Tegra XHCI controller ELPG support
To:     Thierry Reding <thierry.reding@gmail.com>
CC:     <gregkh@linuxfoundation.org>, <robh@kernel.org>,
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References: <20200909081041.3190157-1-jckuo@nvidia.com>
 <20200928125438.GC3065790@ulmo>
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From:   JC Kuo <jckuo@nvidia.com>
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Date:   Wed, 14 Oct 2020 10:26:44 +0800
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Yes, it's safe to apply "clk: tegra: Don't enable PLLE HW sequencer at init"
before the others have applied. Disabling PLLE hardware power sequencer will not
cause any functionality problem to XUSB/PCIE/SATA. The only thing changed is
PLLE won't be powered off by hardware when all clients are in low power state,
i.e., software has to explicitly power off PLLE.

Thanks for review.
JC

On 9/28/20 8:54 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote:
>> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
>> state for power saving when all of the connected USB devices are in
>> suspended state. This patch series includes clk, phy and pmc changes
>> that are required for properly place controller in ELPG and bring
>> controller out of ELPG.
>>
>> JC Kuo (15):
>>   clk: tegra: Add PLLE HW power sequencer control
>>   clk: tegra: Don't enable PLLE HW sequencer at init
> 
> Is it safe to apply this second patch before the others have applied?
> Since we now need to explicitly enable the HW sequencer, it won't be
> enabled before the corresponding patch does that. So applying patch 2
> before the others sounds like it would break existing users of the HW
> sequencer.
> 
> Thierry
>