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* [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support
@ 2020-01-03  8:18 JC Kuo
  2020-01-03  8:18 ` [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config JC Kuo
                   ` (4 more replies)
  0 siblings, 5 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

This series introduces support for Tegra194 XUSB host and pad
controller. Tegra194 XUSB host and pad controller are highly
similar to the controllers found on Tegra186. Therefore, it's
possible to resue xhci-tegra.c and xusb-tegra186.c for Tegra194.

Changelog:
v5:
  phy: tegra: xusb: Protect Tegra186 soc with config
   - no change

  phy: tegra: xusb: Add Tegra194 support
   - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"

  dt-bindings: phy: tegra: Add Tegra194 support
   - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"

  arm64: tegra: Add XUSB and pad controller on Tegra194
   - no change

  arm64: tegra: Enable XUSB host in P2972-0000 board
   - no change

v4:
  xhci: tegra: Parameterize mailbox register addresses
   - removed from v4 as it has been accepted in v3
  
  usb: host: xhci-tegra: Add Tegra194 XHCI support
   - removed from v4 as it has been accepted in v3

  phy: tegra: xusb: Add Tegra194 support
   - no change

  dt-bindings: phy: tegra: Add Tegra194 support
   - no change

  arm64: tegra: Add XUSB and pad controller on Tegra194
   - no change

  arm64: tegra: Enable XUSB host in P2972-0000 board
   - no change

v3:
  add change log to cover latter

v2:
  xhci: tegra: Parameterize mailbox register addresses
   - no change

  usb: host: xhci-tegra: Add Tegra194 XHCI support
   - no change

  phy: tegra: xusb: Protect Tegra186 soc with config
   - new patch to protect Tegra186 soc data with config

  phy: tegra: xusb: Add Tegra194 support
   - removed unnecessary #if/#endif pairs
   - introduce new soc->supports_gen2 flag which indicate whether or not
     a soc supports USB 3.1 Gen 2 speed

  dt-bindings: phy: tegra: Add Tegra194 support
   - fix a typo

  arm64: tegra: Add XUSB and pad controller on Tegra194
   - renamed xhci@3610000 with usb@3610000
   - moved padctl@3520000 and usb@3610000 inside /cbb
   - cleaned up "clocks" property of usb@3610000 node
   - added blanks lines to visually separate blocks

  arm64: tegra: Enable XUSB host in P2972-0000 board
   - use capitalization of regulator names
   - fix gpio property of VDD_5V_SATA regulator

JC Kuo (5):
  phy: tegra: xusb: Protect Tegra186 soc with config
  phy: tegra: xusb: Add Tegra194 support
  dt-bindings: phy: tegra: Add Tegra194 support
  arm64: tegra: Add XUSB and pad controller on Tegra194
  arm64: tegra: Enable XUSB host in P2972-0000 board

 .../phy/nvidia,tegra124-xusb-padctl.txt       |  18 +++
 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi |  36 ++++-
 .../boot/dts/nvidia/tegra194-p2972-0000.dts   |  63 ++++++++
 arch/arm64/boot/dts/nvidia/tegra194.dtsi      | 139 +++++++++++++++++
 drivers/phy/tegra/Makefile                    |   1 +
 drivers/phy/tegra/xusb-tegra186.c             | 143 +++++++++++++-----
 drivers/phy/tegra/xusb.c                      |  17 +++
 drivers/phy/tegra/xusb.h                      |   5 +
 8 files changed, 387 insertions(+), 35 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config
  2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
@ 2020-01-03  8:18 ` JC Kuo
  2020-01-03  8:18 ` [PATCH v5 2/5] phy: tegra: xusb: Add Tegra194 support JC Kuo
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

As xusb-tegra186.c will be reused for Tegra194, it would be good to
protect Tegra186 soc data with CONFIG_ARCH_TEGRA_186_SOC. This commit
also reshuffles Tegra186 soc data single CONFIG_ARCH_TEGRA_186_SOC
will be sufficient.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- new patch to protect Tegra186 soc data with config

 drivers/phy/tegra/xusb-tegra186.c | 70 ++++++++++++++++---------------
 1 file changed, 36 insertions(+), 34 deletions(-)

diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 84c27394c181..01f7d979c9a8 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -503,19 +503,6 @@ static const char * const tegra186_usb2_functions[] = {
 	"xusb",
 };
 
-static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
-	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
-	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
-	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
-};
-
-static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
-	.name = "usb2",
-	.num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
-	.lanes = tegra186_usb2_lanes,
-	.ops = &tegra186_usb2_pad_ops,
-};
-
 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
 {
 	return 0;
@@ -765,27 +752,6 @@ static const char * const tegra186_usb3_functions[] = {
 	"xusb",
 };
 
-static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
-	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
-	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
-	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
-};
-
-static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
-	.name = "usb3",
-	.num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
-	.lanes = tegra186_usb3_lanes,
-	.ops = &tegra186_usb3_pad_ops,
-};
-
-static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
-	&tegra186_usb2_pad,
-	&tegra186_usb3_pad,
-#if 0 /* TODO implement */
-	&tegra186_hsic_pad,
-#endif
-};
-
 static int
 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
 {
@@ -885,6 +851,7 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
 	.vbus_override = tegra186_xusb_padctl_vbus_override,
 };
 
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
 static const char * const tegra186_xusb_padctl_supply_names[] = {
 	"avdd-pll-erefeut",
 	"avdd-usb",
@@ -892,6 +859,40 @@ static const char * const tegra186_xusb_padctl_supply_names[] = {
 	"vddio-hsic",
 };
 
+static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
+	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
+	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
+	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
+};
+
+static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
+	.name = "usb2",
+	.num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
+	.lanes = tegra186_usb2_lanes,
+	.ops = &tegra186_usb2_pad_ops,
+};
+
+static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
+	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
+	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
+	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
+};
+
+static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
+	.name = "usb3",
+	.num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
+	.lanes = tegra186_usb3_lanes,
+	.ops = &tegra186_usb3_pad_ops,
+};
+
+static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
+	&tegra186_usb2_pad,
+	&tegra186_usb3_pad,
+#if 0 /* TODO implement */
+	&tegra186_hsic_pad,
+#endif
+};
+
 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
 	.num_pads = ARRAY_SIZE(tegra186_pads),
 	.pads = tegra186_pads,
@@ -916,6 +917,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
 	.num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
 };
 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
+#endif
 
 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v5 2/5] phy: tegra: xusb: Add Tegra194 support
  2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
  2020-01-03  8:18 ` [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config JC Kuo
@ 2020-01-03  8:18 ` JC Kuo
  2020-01-03  8:18 ` [PATCH v5 3/5] dt-bindings: phy: tegra: " JC Kuo
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

Add support for the XUSB pad controller found on Tegra194 SoCs. It is
mostly similar to the same IP found on Tegra186, but the number of
pads exposed differs, as do the programming sequences. Because most of
the Tegra194 XUSB PADCTL registers definition and programming sequence
are the same as Tegra186, Tegra194 XUSB PADCTL can share the same
driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL.

Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
is possible for some platforms have long signal trace that could not
provide sufficient electrical environment for Gen 2 speed. This patch
adds a "maximum-speed" property to usb3 ports which can be used to
specify the maximum supported speed for any particular USB 3.1 port.
For a port that is not capable of SuperSpeedPlus, "maximum-speed"
property should carry "super-speed".

Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
Changes in v4: none
Changes in v3: none
Changes in v2:
- removed unnecessary #if/#endif pairs
- introduce new soc->supports_gen2 flag which indicate whether or not
  a soc supports USB 3.1 Gen 2 speed

 drivers/phy/tegra/Makefile        |  1 +
 drivers/phy/tegra/xusb-tegra186.c | 73 +++++++++++++++++++++++++++++++
 drivers/phy/tegra/xusb.c          | 17 +++++++
 drivers/phy/tegra/xusb.h          |  5 +++
 4 files changed, 96 insertions(+)

diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
index 320dd389f34d..89b84067cb4c 100644
--- a/drivers/phy/tegra/Makefile
+++ b/drivers/phy/tegra/Makefile
@@ -6,4 +6,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
+phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
 obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 01f7d979c9a8..f16016dcd260 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -63,6 +63,10 @@
 #define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
 #define  SSPX_ELPG_CLAMP_EN_EARLY(x)		BIT(1 + (x) * 3)
 #define  SSPX_ELPG_VCORE_DOWN(x)		BIT(2 + (x) * 3)
+#define XUSB_PADCTL_SS_PORT_CFG			0x2c
+#define   PORTX_SPEED_SUPPORT_SHIFT(x)		((x) * 4)
+#define   PORTX_SPEED_SUPPORT_MASK		(0x3)
+#define     PORT_SPEED_SUPPORT_GEN1		(0x0)
 
 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
 #define  HS_CURR_LEVEL(x)			((x) & 0x3f)
@@ -622,6 +626,15 @@ static int tegra186_usb3_phy_power_on(struct phy *phy)
 
 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
 
+	if (padctl->soc->supports_gen2 && port->disable_gen2) {
+		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
+		value &= ~(PORTX_SPEED_SUPPORT_MASK <<
+			PORTX_SPEED_SUPPORT_SHIFT(index));
+		value |= (PORT_SPEED_SUPPORT_GEN1 <<
+			PORTX_SPEED_SUPPORT_SHIFT(index));
+		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
+	}
+
 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
 	value &= ~SSPX_ELPG_VCORE_DOWN(index);
 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
@@ -919,6 +932,66 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
 #endif
 
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
+static const char * const tegra194_xusb_padctl_supply_names[] = {
+	"avdd-usb",
+	"vclamp-usb",
+};
+
+static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
+	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
+	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
+	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
+	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
+};
+
+static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
+	.name = "usb2",
+	.num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
+	.lanes = tegra194_usb2_lanes,
+	.ops = &tegra186_usb2_pad_ops,
+};
+
+static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
+	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
+	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
+	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
+	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
+};
+
+static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
+	.name = "usb3",
+	.num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
+	.lanes = tegra194_usb3_lanes,
+	.ops = &tegra186_usb3_pad_ops,
+};
+
+static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
+	&tegra194_usb2_pad,
+	&tegra194_usb3_pad,
+};
+
+const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
+	.num_pads = ARRAY_SIZE(tegra194_pads),
+	.pads = tegra194_pads,
+	.ports = {
+		.usb2 = {
+			.ops = &tegra186_usb2_port_ops,
+			.count = 4,
+		},
+		.usb3 = {
+			.ops = &tegra186_usb3_port_ops,
+			.count = 4,
+		},
+	},
+	.ops = &tegra186_xusb_padctl_ops,
+	.supply_names = tegra194_xusb_padctl_supply_names,
+	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
+	.supports_gen2 = true,
+};
+EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
+#endif
+
 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index f98ec3922c02..90b8fb187cf4 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -65,6 +65,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = {
 		.compatible = "nvidia,tegra186-xusb-padctl",
 		.data = &tegra186_xusb_padctl_soc,
 	},
+#endif
+#if defined(CONFIG_ARCH_TEGRA_194_SOC)
+	{
+		.compatible = "nvidia,tegra194-xusb-padctl",
+		.data = &tegra194_xusb_padctl_soc,
+	},
 #endif
 	{ }
 };
@@ -726,6 +732,7 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3)
 {
 	struct tegra_xusb_port *port = &usb3->base;
 	struct device_node *np = port->dev.of_node;
+	enum usb_device_speed maximum_speed;
 	u32 value;
 	int err;
 
@@ -739,6 +746,16 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3)
 
 	usb3->internal = of_property_read_bool(np, "nvidia,internal");
 
+	if (device_property_present(&port->dev, "maximum-speed")) {
+		maximum_speed =  usb_get_maximum_speed(&port->dev);
+		if (maximum_speed == USB_SPEED_SUPER)
+			usb3->disable_gen2 = true;
+		else if (maximum_speed == USB_SPEED_SUPER_PLUS)
+			usb3->disable_gen2 = false;
+		else
+			return -EINVAL;
+	}
+
 	usb3->supply = devm_regulator_get(&port->dev, "vbus");
 	return PTR_ERR_OR_ZERO(usb3->supply);
 }
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index da94fcce6307..e2152d4f1dbf 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -333,6 +333,7 @@ struct tegra_xusb_usb3_port {
 	bool context_saved;
 	unsigned int port;
 	bool internal;
+	bool disable_gen2;
 
 	u32 tap1;
 	u32 amp;
@@ -392,6 +393,7 @@ struct tegra_xusb_padctl_soc {
 
 	const char * const *supply_names;
 	unsigned int num_supplies;
+	bool supports_gen2;
 	bool need_fake_usb3_port;
 };
 
@@ -448,5 +450,8 @@ extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;
 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;
 #endif
+#if defined(CONFIG_ARCH_TEGRA_194_SOC)
+extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
+#endif
 
 #endif /* __PHY_TEGRA_XUSB_H */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
  2020-01-03  8:18 ` [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config JC Kuo
  2020-01-03  8:18 ` [PATCH v5 2/5] phy: tegra: xusb: Add Tegra194 support JC Kuo
@ 2020-01-03  8:18 ` " JC Kuo
  2020-01-03 22:39   ` Rob Herring
  2020-01-03  8:18 ` [PATCH v5 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194 JC Kuo
  2020-01-03  8:18 ` [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board JC Kuo
  4 siblings, 1 reply; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

Extend the bindings to cover the set of features found in Tegra194.
Note that, technically, there are four more supplies connected to the
XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
, but the power sequencing requirements of Tegra194 require these to be
under the control of the PMIC.

Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
is possible for some platforms have long signal trace that could not
provide sufficient electrical environment for Gen 2 speed. This patch
adds a "maximum-speed" property to usb3 ports which can be used to
specify the maximum supported speed for any particular USB 3.1 port.
For a port that is not capable of SuperSpeedPlus, "maximum-speed"
property should carry "super-speed".

Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
Changes in v4: none
Changes in v3: none
Changes in v2:
- fix a typo

 .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
index 9fb682e47c29..7d0089006e67 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
@@ -37,6 +37,7 @@ Required properties:
   - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
   - Tegra210: "nvidia,tegra210-xusb-padctl"
   - Tegra186: "nvidia,tegra186-xusb-padctl"
+  - Tegra194: "nvidia,tegra194-xusb-padctl"
 - reg: Physical base address and length of the controller's registers.
 - resets: Must contain an entry for each entry in reset-names.
 - reset-names: Must include the following entries:
@@ -62,6 +63,10 @@ For Tegra186:
 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
 
+For Tegra194:
+- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
+  3.3 V.
+- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
 
 Pad nodes:
 ==========
@@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
 - sata: sata-0
   - functions: "usb3-ss", "sata"
 
+For Tegra194, the list of valid PHY nodes is given below:
+- usb2: usb2-0, usb2-1, usb2-2, usb2-3
+  - functions: "xusb"
+- usb3: usb3-0, usb3-1, usb3-2, usb3-3
+  - functions: "xusb"
 
 Port nodes:
 ===========
@@ -221,6 +231,11 @@ Optional properties:
   is internal. In the absence of this property the port is considered to be
   external.
 
+- maximum-speed: Only for Tegra194. A string property that specifies maximum
+  supported speed of a usb3 port. Valid values are:
+  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
+  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
+
 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
 ports:
 - 3x USB2: usb2-0, usb2-1, usb2-2
@@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
 - 2x HSIC: hsic-0, hsic-1
 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
 
+For Tegra194, the XUSB pad controller exposes the following ports:
+- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
+- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
 
 Examples:
 =========
-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v5 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194
  2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
                   ` (2 preceding siblings ...)
  2020-01-03  8:18 ` [PATCH v5 3/5] dt-bindings: phy: tegra: " JC Kuo
@ 2020-01-03  8:18 ` JC Kuo
  2020-01-03  8:18 ` [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board JC Kuo
  4 siblings, 0 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

Adds the XUSB pad and XUSB controllers on Tegra194.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
 - renamed xhci@3610000 with usb@3610000
 - moved padctl@3520000 and usb@3610000 inside /cbb
 - cleaned up "clocks" property of usb@3610000 node
 - added blanks lines to visually separate blocks

 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 11220d97adb8..495f692e6a0b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -488,6 +488,145 @@
 			status = "disabled";
 		};
 
+		xusb_padctl: padctl@3520000 {
+			compatible = "nvidia,tegra194-xusb-padctl";
+			reg = <0x03520000 0x1000>,
+			      <0x03540000 0x1000>;
+			reg-names = "padctl", "ao";
+
+			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
+			reset-names = "padctl";
+
+			status = "disabled";
+
+			pads {
+				usb2 {
+					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
+					clock-names = "trk";
+
+					lanes {
+						usb2-0 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb2-1 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb2-2 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb2-3 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb3-1 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb3-2 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						usb3-3 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					status = "disabled";
+				};
+
+				usb2-1 {
+					status = "disabled";
+				};
+
+				usb2-2 {
+					status = "disabled";
+				};
+
+				usb2-3 {
+					status = "disabled";
+				};
+
+				usb3-0 {
+					status = "disabled";
+				};
+
+				usb3-1 {
+					status = "disabled";
+				};
+
+				usb3-2 {
+					status = "disabled";
+				};
+
+				usb3-3 {
+					status = "disabled";
+				};
+			};
+		};
+
+		usb@3610000 {
+			compatible = "nvidia,tegra194-xusb";
+			reg = <0x03610000 0x40000>,
+			      < 0x03600000 0x10000>;
+			reg-names = "hcd", "fpci";
+
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
+				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
+				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
+				 <&bpmp TEGRA194_CLK_XUSB_SS>,
+				 <&bpmp TEGRA194_CLK_CLK_M>,
+				 <&bpmp TEGRA194_CLK_XUSB_FS>,
+				 <&bpmp TEGRA194_CLK_UTMIPLL>,
+				 <&bpmp TEGRA194_CLK_CLK_M>,
+				 <&bpmp TEGRA194_CLK_PLLE>;
+			clock-names = "xusb_host", "xusb_falcon_src",
+				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
+				      "xusb_fs_src", "pll_u_480m", "clk_m",
+				      "pll_e";
+
+			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
+					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
+			power-domain-names = "xusb_host", "xusb_ss";
+
+			nvidia,xusb-padctl = <&xusb_padctl>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@3881000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board
  2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
                   ` (3 preceding siblings ...)
  2020-01-03  8:18 ` [PATCH v5 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194 JC Kuo
@ 2020-01-03  8:18 ` JC Kuo
  4 siblings, 0 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-03  8:18 UTC (permalink / raw)
  To: gregkh, thierry.reding, robh, jonathanh, kishon
  Cc: linux-tegra, linux-usb, linux-kernel, devicetree, nkristam, JC Kuo

This commit enables XUSB host and pad controller in Tegra194
P2972-0000 board.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- use capitalization of regulator names
- fix gpio property of VDD_5V_SATA regulator

 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++-
 .../boot/dts/nvidia/tegra194-p2972-0000.dts   | 63 +++++++++++++++++++
 2 files changed, 98 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index c7f2a20e6b02..014e18b2d52a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -67,6 +67,29 @@
 			vmmc-supply = <&vdd_emmc_3v3>;
 		};
 
+		padctl@3520000 {
+			avdd-usb-supply = <&vdd_usb_3v3>;
+			vclamp-usb-supply = <&vdd_1v8ao>;
+
+			ports {
+				usb2-1 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-3 {
+					vbus-supply = <&vdd_5v_sata>;
+				};
+
+				usb3-0 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb3-3 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+			};
+		};
+
 		rtc@c2a0000 {
 			status = "okay";
 		};
@@ -230,7 +253,7 @@
 						regulator-max-microvolt = <3300000>;
 					};
 
-					ldo5 {
+					vdd_usb_3v3: ldo5 {
 						regulator-name = "VDD_USB_3V3";
 						regulator-min-microvolt = <3300000>;
 						regulator-max-microvolt = <3300000>;
@@ -313,5 +336,16 @@
 			gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
 			regulator-boot-on;
 		};
+
+		vdd_5v_sata: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+
+			regulator-name = "VDD_5V_SATA";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 353a6a22196d..2cbcae39d1b0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -37,6 +37,69 @@
 			status = "okay";
 		};
 
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-1 {
+							status = "okay";
+						};
+
+						usb2-3 {
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							status = "okay";
+						};
+
+						usb3-3 {
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-1 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+
+				usb3-3 {
+					nvidia,usb2-companion = <3>;
+					nvidia,disable-gen2;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3610000 {
+			status = "okay";
+
+			phys =	<&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+				<&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+				<&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+				<&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
+			phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3";
+		};
+
 		pwm@c340000 {
 			status = "okay";
 		};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-03  8:18 ` [PATCH v5 3/5] dt-bindings: phy: tegra: " JC Kuo
@ 2020-01-03 22:39   ` Rob Herring
  2020-01-06  7:10     ` JC Kuo
  0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2020-01-03 22:39 UTC (permalink / raw)
  To: JC Kuo
  Cc: gregkh, thierry.reding, jonathanh, kishon, linux-tegra,
	linux-usb, linux-kernel, devicetree, nkristam

On Fri, Jan 03, 2020 at 04:18:12PM +0800, JC Kuo wrote:
> Extend the bindings to cover the set of features found in Tegra194.
> Note that, technically, there are four more supplies connected to the
> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
> , but the power sequencing requirements of Tegra194 require these to be
> under the control of the PMIC.
> 
> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
> is possible for some platforms have long signal trace that could not
> provide sufficient electrical environment for Gen 2 speed. This patch
> adds a "maximum-speed" property to usb3 ports which can be used to
> specify the maximum supported speed for any particular USB 3.1 port.
> For a port that is not capable of SuperSpeedPlus, "maximum-speed"
> property should carry "super-speed".
> 
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> Changes in v5:
> - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
> Changes in v4: none
> Changes in v3: none
> Changes in v2:
> - fix a typo
> 
>  .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> index 9fb682e47c29..7d0089006e67 100644
> --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> @@ -37,6 +37,7 @@ Required properties:
>    - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
>    - Tegra210: "nvidia,tegra210-xusb-padctl"
>    - Tegra186: "nvidia,tegra186-xusb-padctl"
> +  - Tegra194: "nvidia,tegra194-xusb-padctl"
>  - reg: Physical base address and length of the controller's registers.
>  - resets: Must contain an entry for each entry in reset-names.
>  - reset-names: Must include the following entries:
> @@ -62,6 +63,10 @@ For Tegra186:
>  - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>  - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
>  
> +For Tegra194:
> +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
> +  3.3 V.
> +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>  
>  Pad nodes:
>  ==========
> @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
>  - sata: sata-0
>    - functions: "usb3-ss", "sata"
>  
> +For Tegra194, the list of valid PHY nodes is given below:
> +- usb2: usb2-0, usb2-1, usb2-2, usb2-3
> +  - functions: "xusb"
> +- usb3: usb3-0, usb3-1, usb3-2, usb3-3
> +  - functions: "xusb"
>  
>  Port nodes:
>  ===========
> @@ -221,6 +231,11 @@ Optional properties:
>    is internal. In the absence of this property the port is considered to be
>    external.
>  
> +- maximum-speed: Only for Tegra194. A string property that specifies maximum
> +  supported speed of a usb3 port. Valid values are:
> +  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.

Not defined as a valid value in usb/generic.txt. '-gen2' instead of 
'-plus' would be clearer IMO. However, is there any need to define the 
maximum speed possible? The purpose of this property is to limit the 
speed below the max.

> +  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
> +
>  For Tegra124 and Tegra132, the XUSB pad controller exposes the following
>  ports:
>  - 3x USB2: usb2-0, usb2-1, usb2-2
> @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
>  - 2x HSIC: hsic-0, hsic-1
>  - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>  
> +For Tegra194, the XUSB pad controller exposes the following ports:
> +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
> +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>  
>  Examples:
>  =========
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-03 22:39   ` Rob Herring
@ 2020-01-06  7:10     ` JC Kuo
  2020-01-09  1:31       ` JC Kuo
  0 siblings, 1 reply; 11+ messages in thread
From: JC Kuo @ 2020-01-06  7:10 UTC (permalink / raw)
  To: Rob Herring
  Cc: gregkh, thierry.reding, jonathanh, kishon, linux-tegra,
	linux-usb, linux-kernel, devicetree, nkristam

On 1/4/20 6:39 AM, Rob Herring wrote:
> On Fri, Jan 03, 2020 at 04:18:12PM +0800, JC Kuo wrote:
>> Extend the bindings to cover the set of features found in Tegra194.
>> Note that, technically, there are four more supplies connected to the
>> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
>> , but the power sequencing requirements of Tegra194 require these to be
>> under the control of the PMIC.
>>
>> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
>> is possible for some platforms have long signal trace that could not
>> provide sufficient electrical environment for Gen 2 speed. This patch
>> adds a "maximum-speed" property to usb3 ports which can be used to
>> specify the maximum supported speed for any particular USB 3.1 port.
>> For a port that is not capable of SuperSpeedPlus, "maximum-speed"
>> property should carry "super-speed".
>>
>> Signed-off-by: JC Kuo <jckuo@nvidia.com>
>> ---
>> Changes in v5:
>> - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
>> Changes in v4: none
>> Changes in v3: none
>> Changes in v2:
>> - fix a typo
>>
>>  .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>> index 9fb682e47c29..7d0089006e67 100644
>> --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>> @@ -37,6 +37,7 @@ Required properties:
>>    - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
>>    - Tegra210: "nvidia,tegra210-xusb-padctl"
>>    - Tegra186: "nvidia,tegra186-xusb-padctl"
>> +  - Tegra194: "nvidia,tegra194-xusb-padctl"
>>  - reg: Physical base address and length of the controller's registers.
>>  - resets: Must contain an entry for each entry in reset-names.
>>  - reset-names: Must include the following entries:
>> @@ -62,6 +63,10 @@ For Tegra186:
>>  - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>  - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
>>  
>> +For Tegra194:
>> +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
>> +  3.3 V.
>> +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>  
>>  Pad nodes:
>>  ==========
>> @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
>>  - sata: sata-0
>>    - functions: "usb3-ss", "sata"
>>  
>> +For Tegra194, the list of valid PHY nodes is given below:
>> +- usb2: usb2-0, usb2-1, usb2-2, usb2-3
>> +  - functions: "xusb"
>> +- usb3: usb3-0, usb3-1, usb3-2, usb3-3
>> +  - functions: "xusb"
>>  
>>  Port nodes:
>>  ===========
>> @@ -221,6 +231,11 @@ Optional properties:
>>    is internal. In the absence of this property the port is considered to be
>>    external.
>>  
>> +- maximum-speed: Only for Tegra194. A string property that specifies maximum
>> +  supported speed of a usb3 port. Valid values are:
>> +  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
> 
> Not defined as a valid value in usb/generic.txt. '-gen2' instead of 
> '-plus' would be clearer IMO. However, is there any need to define the 
> maximum speed possible? The purpose of this property is to limit the 
> speed below the max.
> 
usb_get_maximum_speed(), which parses "maximum-speed" property, indeed handles
string "super-speed-plus". Should "super-speed-plus" be documented in
usb/generic.txt"?

static const char *const speed_names[] = {
	[USB_SPEED_UNKNOWN] = "UNKNOWN",
	[USB_SPEED_LOW] = "low-speed",
	[USB_SPEED_FULL] = "full-speed",
	[USB_SPEED_HIGH] = "high-speed",
	[USB_SPEED_WIRELESS] = "wireless",
	[USB_SPEED_SUPER] = "super-speed",
	[USB_SPEED_SUPER_PLUS] = "super-speed-plus",
};

A proprietary "nvidia,disable-gen2" property was proposed in earlier revision to
"limit the speed below the max". I like it because it fit our needs better and
requires only one line of code change.

   usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");

Should I fallback to that approach?

Thanks,
JC

>> +  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
>> +
>>  For Tegra124 and Tegra132, the XUSB pad controller exposes the following
>>  ports:
>>  - 3x USB2: usb2-0, usb2-1, usb2-2
>> @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
>>  - 2x HSIC: hsic-0, hsic-1
>>  - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>  
>> +For Tegra194, the XUSB pad controller exposes the following ports:
>> +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
>> +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>  
>>  Examples:
>>  =========
>> -- 
>> 2.17.1
>>

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-06  7:10     ` JC Kuo
@ 2020-01-09  1:31       ` JC Kuo
  2020-01-10 11:26         ` Thierry Reding
  0 siblings, 1 reply; 11+ messages in thread
From: JC Kuo @ 2020-01-09  1:31 UTC (permalink / raw)
  To: Rob Herring
  Cc: gregkh, thierry.reding, jonathanh, kishon, linux-tegra,
	linux-usb, linux-kernel, devicetree, nkristam

Hi Rob,
For now we have two options.
1. reusing the existing "maximum-speed" which is documented in usb/generic.txt
Pro: no need to add new property
Con: only "super-speed" and "super-speed-plus" are valid for Tegra XUSB PADCTL,
therefore extra code/document change is required.

+	if (device_property_present(&port->dev, "maximum-speed")) {
+		maximum_speed =  usb_get_maximum_speed(&port->dev);
+		if (maximum_speed == USB_SPEED_SUPER)
+			usb3->disable_gen2 = true;
+		else if (maximum_speed == USB_SPEED_SUPER_PLUS)
+			usb3->disable_gen2 = false;
+		else
+			return -EINVAL;
+	}

2. introducing a new proprietary "nvidia,disable-gen2" property
Pro: its logic perfectly matches the need, and code change is minimum

+        usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");

Con: it's a new and proprietary property.

Please let me know which one do you prefer or there is something else works better.

Thanks,
JC


On 1/6/20 3:10 PM, JC Kuo wrote:
> On 1/4/20 6:39 AM, Rob Herring wrote:
>> On Fri, Jan 03, 2020 at 04:18:12PM +0800, JC Kuo wrote:
>>> Extend the bindings to cover the set of features found in Tegra194.
>>> Note that, technically, there are four more supplies connected to the
>>> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
>>> , but the power sequencing requirements of Tegra194 require these to be
>>> under the control of the PMIC.
>>>
>>> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
>>> is possible for some platforms have long signal trace that could not
>>> provide sufficient electrical environment for Gen 2 speed. This patch
>>> adds a "maximum-speed" property to usb3 ports which can be used to
>>> specify the maximum supported speed for any particular USB 3.1 port.
>>> For a port that is not capable of SuperSpeedPlus, "maximum-speed"
>>> property should carry "super-speed".
>>>
>>> Signed-off-by: JC Kuo <jckuo@nvidia.com>
>>> ---
>>> Changes in v5:
>>> - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
>>> Changes in v4: none
>>> Changes in v3: none
>>> Changes in v2:
>>> - fix a typo
>>>
>>>  .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
>>>  1 file changed, 18 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>> index 9fb682e47c29..7d0089006e67 100644
>>> --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>> @@ -37,6 +37,7 @@ Required properties:
>>>    - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
>>>    - Tegra210: "nvidia,tegra210-xusb-padctl"
>>>    - Tegra186: "nvidia,tegra186-xusb-padctl"
>>> +  - Tegra194: "nvidia,tegra194-xusb-padctl"
>>>  - reg: Physical base address and length of the controller's registers.
>>>  - resets: Must contain an entry for each entry in reset-names.
>>>  - reset-names: Must include the following entries:
>>> @@ -62,6 +63,10 @@ For Tegra186:
>>>  - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>>  - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
>>>  
>>> +For Tegra194:
>>> +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
>>> +  3.3 V.
>>> +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>>  
>>>  Pad nodes:
>>>  ==========
>>> @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
>>>  - sata: sata-0
>>>    - functions: "usb3-ss", "sata"
>>>  
>>> +For Tegra194, the list of valid PHY nodes is given below:
>>> +- usb2: usb2-0, usb2-1, usb2-2, usb2-3
>>> +  - functions: "xusb"
>>> +- usb3: usb3-0, usb3-1, usb3-2, usb3-3
>>> +  - functions: "xusb"
>>>  
>>>  Port nodes:
>>>  ===========
>>> @@ -221,6 +231,11 @@ Optional properties:
>>>    is internal. In the absence of this property the port is considered to be
>>>    external.
>>>  
>>> +- maximum-speed: Only for Tegra194. A string property that specifies maximum
>>> +  supported speed of a usb3 port. Valid values are:
>>> +  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
>>
>> Not defined as a valid value in usb/generic.txt. '-gen2' instead of 
>> '-plus' would be clearer IMO. However, is there any need to define the 
>> maximum speed possible? The purpose of this property is to limit the 
>> speed below the max.
>>
> usb_get_maximum_speed(), which parses "maximum-speed" property, indeed handles
> string "super-speed-plus". Should "super-speed-plus" be documented in
> usb/generic.txt"?
> 
> static const char *const speed_names[] = {
> 	[USB_SPEED_UNKNOWN] = "UNKNOWN",
> 	[USB_SPEED_LOW] = "low-speed",
> 	[USB_SPEED_FULL] = "full-speed",
> 	[USB_SPEED_HIGH] = "high-speed",
> 	[USB_SPEED_WIRELESS] = "wireless",
> 	[USB_SPEED_SUPER] = "super-speed",
> 	[USB_SPEED_SUPER_PLUS] = "super-speed-plus",
> };
> 
> A proprietary "nvidia,disable-gen2" property was proposed in earlier revision to
> "limit the speed below the max". I like it because it fit our needs better and
> requires only one line of code change.
> 
>    usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");
> 
> Should I fallback to that approach?
> 
> Thanks,
> JC
> 
>>> +  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
>>> +
>>>  For Tegra124 and Tegra132, the XUSB pad controller exposes the following
>>>  ports:
>>>  - 3x USB2: usb2-0, usb2-1, usb2-2
>>> @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
>>>  - 2x HSIC: hsic-0, hsic-1
>>>  - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>>  
>>> +For Tegra194, the XUSB pad controller exposes the following ports:
>>> +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
>>> +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>>  
>>>  Examples:
>>>  =========
>>> -- 
>>> 2.17.1
>>>

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-09  1:31       ` JC Kuo
@ 2020-01-10 11:26         ` Thierry Reding
  2020-01-13  2:15           ` JC Kuo
  0 siblings, 1 reply; 11+ messages in thread
From: Thierry Reding @ 2020-01-10 11:26 UTC (permalink / raw)
  To: JC Kuo
  Cc: Rob Herring, gregkh, jonathanh, kishon, linux-tegra, linux-usb,
	linux-kernel, devicetree, nkristam

[-- Attachment #1: Type: text/plain, Size: 7454 bytes --]

On Thu, Jan 09, 2020 at 09:31:27AM +0800, JC Kuo wrote:
> Hi Rob,
> For now we have two options.
> 1. reusing the existing "maximum-speed" which is documented in usb/generic.txt
> Pro: no need to add new property
> Con: only "super-speed" and "super-speed-plus" are valid for Tegra XUSB PADCTL,
> therefore extra code/document change is required.
> 
> +	if (device_property_present(&port->dev, "maximum-speed")) {
> +		maximum_speed =  usb_get_maximum_speed(&port->dev);
> +		if (maximum_speed == USB_SPEED_SUPER)
> +			usb3->disable_gen2 = true;
> +		else if (maximum_speed == USB_SPEED_SUPER_PLUS)
> +			usb3->disable_gen2 = false;
> +		else
> +			return -EINVAL;
> +	}
> 
> 2. introducing a new proprietary "nvidia,disable-gen2" property
> Pro: its logic perfectly matches the need, and code change is minimum
> 
> +        usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");
> 
> Con: it's a new and proprietary property.
> 
> Please let me know which one do you prefer or there is something else
> works better.

I think the first version is much clearer. maximum-speed = "super-speed"
is very clear and explicit. nvidia,disable-gen2 is less so. While it may
be true in this case what "disable-gen2" does, using the generic
bindings has the advantage that it'll be more familiar to people already
familiar with other USB device tree bindings.

Also, the nvidia,disable-gen2 property only perfectly matches the need
because it reflects the name of the variable. If you rewrote the code to
do something like this:

	if (port->maximum_speed <= USB_SPEED_SUPER) {
		/* disable gen2 */
		...
	}

Then all of a sudden the "maximum-speed" property is a perfect match. In
general, bindings should be natural to the domain of the bus or device
that they describe rather than a reflection of how the driver programs
the device's registers.

On a side-note: we should also update the usb/generic.txt binding to
describe the "super-speed-plus" value for the maximum-speed property.

Thierry

> Thanks,
> JC
> 
> 
> On 1/6/20 3:10 PM, JC Kuo wrote:
> > On 1/4/20 6:39 AM, Rob Herring wrote:
> >> On Fri, Jan 03, 2020 at 04:18:12PM +0800, JC Kuo wrote:
> >>> Extend the bindings to cover the set of features found in Tegra194.
> >>> Note that, technically, there are four more supplies connected to the
> >>> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
> >>> , but the power sequencing requirements of Tegra194 require these to be
> >>> under the control of the PMIC.
> >>>
> >>> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
> >>> is possible for some platforms have long signal trace that could not
> >>> provide sufficient electrical environment for Gen 2 speed. This patch
> >>> adds a "maximum-speed" property to usb3 ports which can be used to
> >>> specify the maximum supported speed for any particular USB 3.1 port.
> >>> For a port that is not capable of SuperSpeedPlus, "maximum-speed"
> >>> property should carry "super-speed".
> >>>
> >>> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> >>> ---
> >>> Changes in v5:
> >>> - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
> >>> Changes in v4: none
> >>> Changes in v3: none
> >>> Changes in v2:
> >>> - fix a typo
> >>>
> >>>  .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
> >>>  1 file changed, 18 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> >>> index 9fb682e47c29..7d0089006e67 100644
> >>> --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> >>> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
> >>> @@ -37,6 +37,7 @@ Required properties:
> >>>    - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
> >>>    - Tegra210: "nvidia,tegra210-xusb-padctl"
> >>>    - Tegra186: "nvidia,tegra186-xusb-padctl"
> >>> +  - Tegra194: "nvidia,tegra194-xusb-padctl"
> >>>  - reg: Physical base address and length of the controller's registers.
> >>>  - resets: Must contain an entry for each entry in reset-names.
> >>>  - reset-names: Must include the following entries:
> >>> @@ -62,6 +63,10 @@ For Tegra186:
> >>>  - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
> >>>  - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
> >>>  
> >>> +For Tegra194:
> >>> +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
> >>> +  3.3 V.
> >>> +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
> >>>  
> >>>  Pad nodes:
> >>>  ==========
> >>> @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
> >>>  - sata: sata-0
> >>>    - functions: "usb3-ss", "sata"
> >>>  
> >>> +For Tegra194, the list of valid PHY nodes is given below:
> >>> +- usb2: usb2-0, usb2-1, usb2-2, usb2-3
> >>> +  - functions: "xusb"
> >>> +- usb3: usb3-0, usb3-1, usb3-2, usb3-3
> >>> +  - functions: "xusb"
> >>>  
> >>>  Port nodes:
> >>>  ===========
> >>> @@ -221,6 +231,11 @@ Optional properties:
> >>>    is internal. In the absence of this property the port is considered to be
> >>>    external.
> >>>  
> >>> +- maximum-speed: Only for Tegra194. A string property that specifies maximum
> >>> +  supported speed of a usb3 port. Valid values are:
> >>> +  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
> >>
> >> Not defined as a valid value in usb/generic.txt. '-gen2' instead of 
> >> '-plus' would be clearer IMO. However, is there any need to define the 
> >> maximum speed possible? The purpose of this property is to limit the 
> >> speed below the max.
> >>
> > usb_get_maximum_speed(), which parses "maximum-speed" property, indeed handles
> > string "super-speed-plus". Should "super-speed-plus" be documented in
> > usb/generic.txt"?
> > 
> > static const char *const speed_names[] = {
> > 	[USB_SPEED_UNKNOWN] = "UNKNOWN",
> > 	[USB_SPEED_LOW] = "low-speed",
> > 	[USB_SPEED_FULL] = "full-speed",
> > 	[USB_SPEED_HIGH] = "high-speed",
> > 	[USB_SPEED_WIRELESS] = "wireless",
> > 	[USB_SPEED_SUPER] = "super-speed",
> > 	[USB_SPEED_SUPER_PLUS] = "super-speed-plus",
> > };
> > 
> > A proprietary "nvidia,disable-gen2" property was proposed in earlier revision to
> > "limit the speed below the max". I like it because it fit our needs better and
> > requires only one line of code change.
> > 
> >    usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");
> > 
> > Should I fallback to that approach?
> > 
> > Thanks,
> > JC
> > 
> >>> +  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
> >>> +
> >>>  For Tegra124 and Tegra132, the XUSB pad controller exposes the following
> >>>  ports:
> >>>  - 3x USB2: usb2-0, usb2-1, usb2-2
> >>> @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
> >>>  - 2x HSIC: hsic-0, hsic-1
> >>>  - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
> >>>  
> >>> +For Tegra194, the XUSB pad controller exposes the following ports:
> >>> +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
> >>> +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
> >>>  
> >>>  Examples:
> >>>  =========
> >>> -- 
> >>> 2.17.1
> >>>

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support
  2020-01-10 11:26         ` Thierry Reding
@ 2020-01-13  2:15           ` JC Kuo
  0 siblings, 0 replies; 11+ messages in thread
From: JC Kuo @ 2020-01-13  2:15 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Rob Herring, gregkh, jonathanh, kishon, linux-tegra, linux-usb,
	linux-kernel, devicetree, nkristam

On 1/10/20 7:26 PM, Thierry Reding wrote:
> On Thu, Jan 09, 2020 at 09:31:27AM +0800, JC Kuo wrote:
>> Hi Rob,
>> For now we have two options.
>> 1. reusing the existing "maximum-speed" which is documented in usb/generic.txt
>> Pro: no need to add new property
>> Con: only "super-speed" and "super-speed-plus" are valid for Tegra XUSB PADCTL,
>> therefore extra code/document change is required.
>>
>> +	if (device_property_present(&port->dev, "maximum-speed")) {
>> +		maximum_speed =  usb_get_maximum_speed(&port->dev);
>> +		if (maximum_speed == USB_SPEED_SUPER)
>> +			usb3->disable_gen2 = true;
>> +		else if (maximum_speed == USB_SPEED_SUPER_PLUS)
>> +			usb3->disable_gen2 = false;
>> +		else
>> +			return -EINVAL;
>> +	}
>>
>> 2. introducing a new proprietary "nvidia,disable-gen2" property
>> Pro: its logic perfectly matches the need, and code change is minimum
>>
>> +        usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");
>>
>> Con: it's a new and proprietary property.
>>
>> Please let me know which one do you prefer or there is something else
>> works better.
> 
> I think the first version is much clearer. maximum-speed = "super-speed"
> is very clear and explicit. nvidia,disable-gen2 is less so. While it may
> be true in this case what "disable-gen2" does, using the generic
> bindings has the advantage that it'll be more familiar to people already
> familiar with other USB device tree bindings.
> 
> Also, the nvidia,disable-gen2 property only perfectly matches the need
> because it reflects the name of the variable. If you rewrote the code to
> do something like this:
> 
> 	if (port->maximum_speed <= USB_SPEED_SUPER) {
> 		/* disable gen2 */
> 		...
> 	}

"low-speed/full-speed/high-speed/wireless" options are invalid to a usb3 port
because a usb3 port is not capable of operating at
low-/full-/high-speed/wireless protocols. Therefore,
maximum-speed="low-/full-/high-speed/wireless" is something more like completely
disabling the usb3 port than just disabling super-speed-plus.

I see using an existing "maximum-speed" is preferred. Please review code change
in v5 and let me know if anything could be improved further.

> 
> Then all of a sudden the "maximum-speed" property is a perfect match. In
> general, bindings should be natural to the domain of the bus or device
> that they describe rather than a reflection of how the driver programs
> the device's registers.
> 
> On a side-note: we should also update the usb/generic.txt binding to
> describe the "super-speed-plus" value for the maximum-speed property.
Yes, I feel the same. I will send a patch for it.

Thanks,
JC

> 
> Thierry
> 
>> Thanks,
>> JC
>>
>>
>> On 1/6/20 3:10 PM, JC Kuo wrote:
>>> On 1/4/20 6:39 AM, Rob Herring wrote:
>>>> On Fri, Jan 03, 2020 at 04:18:12PM +0800, JC Kuo wrote:
>>>>> Extend the bindings to cover the set of features found in Tegra194.
>>>>> Note that, technically, there are four more supplies connected to the
>>>>> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
>>>>> , but the power sequencing requirements of Tegra194 require these to be
>>>>> under the control of the PMIC.
>>>>>
>>>>> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
>>>>> is possible for some platforms have long signal trace that could not
>>>>> provide sufficient electrical environment for Gen 2 speed. This patch
>>>>> adds a "maximum-speed" property to usb3 ports which can be used to
>>>>> specify the maximum supported speed for any particular USB 3.1 port.
>>>>> For a port that is not capable of SuperSpeedPlus, "maximum-speed"
>>>>> property should carry "super-speed".
>>>>>
>>>>> Signed-off-by: JC Kuo <jckuo@nvidia.com>
>>>>> ---
>>>>> Changes in v5:
>>>>> - re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
>>>>> Changes in v4: none
>>>>> Changes in v3: none
>>>>> Changes in v2:
>>>>> - fix a typo
>>>>>
>>>>>  .../phy/nvidia,tegra124-xusb-padctl.txt        | 18 ++++++++++++++++++
>>>>>  1 file changed, 18 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>>>> index 9fb682e47c29..7d0089006e67 100644
>>>>> --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>>>> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>>>>> @@ -37,6 +37,7 @@ Required properties:
>>>>>    - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
>>>>>    - Tegra210: "nvidia,tegra210-xusb-padctl"
>>>>>    - Tegra186: "nvidia,tegra186-xusb-padctl"
>>>>> +  - Tegra194: "nvidia,tegra194-xusb-padctl"
>>>>>  - reg: Physical base address and length of the controller's registers.
>>>>>  - resets: Must contain an entry for each entry in reset-names.
>>>>>  - reset-names: Must include the following entries:
>>>>> @@ -62,6 +63,10 @@ For Tegra186:
>>>>>  - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>>>>  - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
>>>>>  
>>>>> +For Tegra194:
>>>>> +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
>>>>> +  3.3 V.
>>>>> +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
>>>>>  
>>>>>  Pad nodes:
>>>>>  ==========
>>>>> @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
>>>>>  - sata: sata-0
>>>>>    - functions: "usb3-ss", "sata"
>>>>>  
>>>>> +For Tegra194, the list of valid PHY nodes is given below:
>>>>> +- usb2: usb2-0, usb2-1, usb2-2, usb2-3
>>>>> +  - functions: "xusb"
>>>>> +- usb3: usb3-0, usb3-1, usb3-2, usb3-3
>>>>> +  - functions: "xusb"
>>>>>  
>>>>>  Port nodes:
>>>>>  ===========
>>>>> @@ -221,6 +231,11 @@ Optional properties:
>>>>>    is internal. In the absence of this property the port is considered to be
>>>>>    external.
>>>>>  
>>>>> +- maximum-speed: Only for Tegra194. A string property that specifies maximum
>>>>> +  supported speed of a usb3 port. Valid values are:
>>>>> +  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
>>>>
>>>> Not defined as a valid value in usb/generic.txt. '-gen2' instead of 
>>>> '-plus' would be clearer IMO. However, is there any need to define the 
>>>> maximum speed possible? The purpose of this property is to limit the 
>>>> speed below the max.
>>>>
>>> usb_get_maximum_speed(), which parses "maximum-speed" property, indeed handles
>>> string "super-speed-plus". Should "super-speed-plus" be documented in
>>> usb/generic.txt"?
>>>
>>> static const char *const speed_names[] = {
>>> 	[USB_SPEED_UNKNOWN] = "UNKNOWN",
>>> 	[USB_SPEED_LOW] = "low-speed",
>>> 	[USB_SPEED_FULL] = "full-speed",
>>> 	[USB_SPEED_HIGH] = "high-speed",
>>> 	[USB_SPEED_WIRELESS] = "wireless",
>>> 	[USB_SPEED_SUPER] = "super-speed",
>>> 	[USB_SPEED_SUPER_PLUS] = "super-speed-plus",
>>> };
>>>
>>> A proprietary "nvidia,disable-gen2" property was proposed in earlier revision to
>>> "limit the speed below the max". I like it because it fit our needs better and
>>> requires only one line of code change.
>>>
>>>    usb3->disable_gen2 = of_property_read_bool(np, "nvidia,disable-gen2");
>>>
>>> Should I fallback to that approach?
>>>
>>> Thanks,
>>> JC
>>>
>>>>> +  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
>>>>> +
>>>>>  For Tegra124 and Tegra132, the XUSB pad controller exposes the following
>>>>>  ports:
>>>>>  - 3x USB2: usb2-0, usb2-1, usb2-2
>>>>> @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
>>>>>  - 2x HSIC: hsic-0, hsic-1
>>>>>  - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>>>>  
>>>>> +For Tegra194, the XUSB pad controller exposes the following ports:
>>>>> +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
>>>>> +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
>>>>>  
>>>>>  Examples:
>>>>>  =========
>>>>> -- 
>>>>> 2.17.1
>>>>>

^ permalink raw reply	[flat|nested] 11+ messages in thread

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Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-03  8:18 [PATCH v5 0/5] add Tegra194 XUSB host and pad controller support JC Kuo
2020-01-03  8:18 ` [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config JC Kuo
2020-01-03  8:18 ` [PATCH v5 2/5] phy: tegra: xusb: Add Tegra194 support JC Kuo
2020-01-03  8:18 ` [PATCH v5 3/5] dt-bindings: phy: tegra: " JC Kuo
2020-01-03 22:39   ` Rob Herring
2020-01-06  7:10     ` JC Kuo
2020-01-09  1:31       ` JC Kuo
2020-01-10 11:26         ` Thierry Reding
2020-01-13  2:15           ` JC Kuo
2020-01-03  8:18 ` [PATCH v5 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194 JC Kuo
2020-01-03  8:18 ` [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board JC Kuo

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