[BUG BISECT] USB on Exynos4412 fails after usb: dwc2: gadget: Replace phyif with phy_utmi_width

[BUG BISECT] USB on Exynos4412 fails after usb: dwc2: gadget: Replace phyif with phy_utmi_width

[Krzysztof Kozlowski]

Hi,

Bisect pointed commit 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif
with phy_utmi_width") as reason for failures of USB on Exynos4412,
Odroid U3 board (ARMv7, exynos_defconfig, TFTP boot with nfsroot from
NFSv4):

[    4.333996] usb 1-2: new high-speed USB device number 3 using exynos-ehci
[    4.503942] usb 1-2: device descriptor read/64, error -71
[    4.793970] usb 1-2: device descriptor read/64, error -71
[    4.914748] usb usb1-port2: attempt power cycle
[    6.224267] usb 1-3: new high-speed USB device number 5 using exynos-ehci
[    6.393983] usb 1-3: device descriptor read/64, error -71
[    6.684243] usb 1-3: device descriptor read/64, error -71
[    6.954259] usb 1-3: new high-speed USB device number 6 using exynos-ehci
[    7.123980] usb 1-3: device descriptor read/64, error -71
[    7.413969] usb 1-3: device descriptor read/64, error -71
[    7.534778] usb usb1-port3: attempt power cycle

The boot failure is effect of lack of network adapter (USB, smsc95xx).
Expected:
[    4.285831] usb 1-3: New USB device found, idVendor=0424, idProduct=3503, bcdDevice=a1.a0
[    4.288986] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    4.299596] hub 1-3:1.0: USB hub found
[    4.300027] hub 1-3:1.0: 3 ports detected
[    5.895541] smsc95xx 1-2:1.0 eth0: link up, 100Mbps, full-duplex, lpa 0xCDE1

Full kernel log is here:
https://krzk.eu/#/builders/25/builds/1330/steps/14/logs/serial0
https://krzk.eu/#/builders/25/builds/1330

Let me know if you need any more details.

Best regards,
Krzysztof

[PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Marek Szyprowski]

Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
host side of the shared USB2 PHY doesn't work.

Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/usb/dwc2/params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 6900eea57526..9ece4affb9d4 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
 	struct dwc2_core_params *p = &hsotg->params;
 
 	p->power_down = 0;
+	p->phy_utmi_width = 8;
 }
 
 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
-- 
2.17.1

Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Jules Maselbas]

Hi,

On Mon, May 06, 2019 at 03:00:46PM +0200, Marek Szyprowski wrote:
> Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
> host side of the shared USB2 PHY doesn't work.
> 
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/usb/dwc2/params.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..9ece4affb9d4 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
>  	struct dwc2_core_params *p = &hsotg->params;
>  
>  	p->power_down = 0;
> +	p->phy_utmi_width = 8;

Nice catch.

I though that 8bits would be the default value, I am curious to know why it's not ny default at 8.

Thanks.


---
Jules

>  }
>  
>  static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
> -- 
> 2.17.1
> 

Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Minas Harutyunyan]

On 5/6/2019 5:01 PM, Marek Szyprowski wrote:
> Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
> host side of the shared USB2 PHY doesn't work.
> 
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Acked-by: Minas Harutyunyan <hminas@synopsys.com>

> ---
>   drivers/usb/dwc2/params.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..9ece4affb9d4 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
>   	struct dwc2_core_params *p = &hsotg->params;
>   
>   	p->power_down = 0;
> +	p->phy_utmi_width = 8;
>   }
>   
>   static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
> 

Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Markus Reichl]

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Hi Marek,

your patch did not help on stable v5.1

[    3.255963] samsung-usb2-phy 125b0000.exynos-usbphy: 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
[    4.044547] usbcore: registered new interface driver smsc95xx
[    4.112261] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.01
[    4.120363] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.127560] usb usb1: Product: EHCI Host Controller
[    4.132415] usb usb1: Manufacturer: Linux 5.1.0-00005-geb4efae48eb5 ehci_hcd
[    4.139446] usb usb1: SerialNumber: 12580000.ehci
[    4.183056] usb3503 0-0008: switched to HUB mode
[    4.183121] usb3503 0-0008: usb3503_probe: probed in hub mode
[    4.488344] usb 1-2: new high-speed USB device number 2 using exynos-ehci
[    4.675605] usb 1-2: New USB device found, idVendor=0424, idProduct=3503, bcdDevice=a1.a0
[    4.678166] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    4.686140] usb 1-2: skipping disabled interface 0

root@odroid-x2:~# lsusb
Bus 001 Device 002: ID 0424:3503 Standard Microsystems Corp.
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub



Am 06.05.19 um 15:00 schrieb Marek Szyprowski:
> Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
> host side of the shared USB2 PHY doesn't work.
> 
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/usb/dwc2/params.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..9ece4affb9d4 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
>  	struct dwc2_core_params *p = &hsotg->params;
>  
>  	p->power_down = 0;
> +	p->phy_utmi_width = 8;
>  }
>  
>  static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
> 

Gruß,
-- 
Markus Reichl


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Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Marek Szyprowski]

Hi Markus,

On 2019-05-07 10:12, Markus Reichl wrote:
> Hi Marek,
>
> your patch did not help on stable v5.1
>
> [    3.255963] samsung-usb2-phy 125b0000.exynos-usbphy: 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
> [    4.044547] usbcore: registered new interface driver smsc95xx
> [    4.112261] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.01
> [    4.120363] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
> [    4.127560] usb usb1: Product: EHCI Host Controller
> [    4.132415] usb usb1: Manufacturer: Linux 5.1.0-00005-geb4efae48eb5 ehci_hcd
> [    4.139446] usb usb1: SerialNumber: 12580000.ehci
> [    4.183056] usb3503 0-0008: switched to HUB mode
> [    4.183121] usb3503 0-0008: usb3503_probe: probed in hub mode
> [    4.488344] usb 1-2: new high-speed USB device number 2 using exynos-ehci
> [    4.675605] usb 1-2: New USB device found, idVendor=0424, idProduct=3503, bcdDevice=a1.a0
> [    4.678166] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> [    4.686140] usb 1-2: skipping disabled interface 0
>
> root@odroid-x2:~# lsusb
> Bus 001 Device 002: ID 0424:3503 Standard Microsystems Corp.
> Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

This patch fixes the issue introduced by "usb: dwc2: gadget: Replace 
phyif with phy_utmi_width" commit, which is queued only to linux-next so 
far. Stable v5.1 doesn't include it, so the fix doesn't change anything 
on v5.1.

I've checked and OdroidU3 works fine with v5.1 release, but X2 fails to 
detect USB devices. I will investigate this in a few minutes...

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Marek Szyprowski]

Hi All,

On 2019-05-07 11:17, Marek Szyprowski wrote:
> Hi Markus,
>
> On 2019-05-07 10:12, Markus Reichl wrote:
>> Hi Marek,
>>
>> your patch did not help on stable v5.1
>>
>> [    3.255963] samsung-usb2-phy 125b0000.exynos-usbphy: 
>> 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
>> [    4.044547] usbcore: registered new interface driver smsc95xx
>> [    4.112261] usb usb1: New USB device found, idVendor=1d6b, 
>> idProduct=0002, bcdDevice= 5.01
>> [    4.120363] usb usb1: New USB device strings: Mfr=3, Product=2, 
>> SerialNumber=1
>> [    4.127560] usb usb1: Product: EHCI Host Controller
>> [    4.132415] usb usb1: Manufacturer: Linux 
>> 5.1.0-00005-geb4efae48eb5 ehci_hcd
>> [    4.139446] usb usb1: SerialNumber: 12580000.ehci
>> [    4.183056] usb3503 0-0008: switched to HUB mode
>> [    4.183121] usb3503 0-0008: usb3503_probe: probed in hub mode
>> [    4.488344] usb 1-2: new high-speed USB device number 2 using 
>> exynos-ehci
>> [    4.675605] usb 1-2: New USB device found, idVendor=0424, 
>> idProduct=3503, bcdDevice=a1.a0
>> [    4.678166] usb 1-2: New USB device strings: Mfr=0, Product=0, 
>> SerialNumber=0
>> [    4.686140] usb 1-2: skipping disabled interface 0
>>
>> root@odroid-x2:~# lsusb
>> Bus 001 Device 002: ID 0424:3503 Standard Microsystems Corp.
>> Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
>
> This patch fixes the issue introduced by "usb: dwc2: gadget: Replace 
> phyif with phy_utmi_width" commit, which is queued only to linux-next 
> so far. Stable v5.1 doesn't include it, so the fix doesn't change 
> anything on v5.1.
>
> I've checked and OdroidU3 works fine with v5.1 release, but X2 fails 
> to detect USB devices. I will investigate this in a few minutes...


Broken USB on X2 is caused by commit 
01fdf179f4b064d4c9d30b39aba178caf32649f4 ("usb: core: skip interfaces 
disabled in devicetree").

I looks that the mentioned commit conflicts with the Exynos EHCI and 
OHCI bindings and the way the PHY ports are defined for those drivers. 
It worked on U3 only by the pure coincidence. This is probably a 
"minimal" fix for this issue:

diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 82239f27c4cc..cd455c4add25 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -2007,6 +2007,7 @@ int usb_set_configuration(struct usb_device *dev, 
int configuration)
                 struct usb_interface *intf = cp->interface[i];

                 if (intf->dev.of_node &&
+                   of_device_is_compatible(intf->dev.of_node, NULL) &&
                     !of_device_is_available(intf->dev.of_node)) {
                         dev_info(&dev->dev, "skipping disabled 
interface %d\n",
intf->cur_altsetting->desc.bInterfaceNumber);

I will try to describe the problem in details and discuss it on the usb 
mailing list.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Markus Reichl]

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Hi Marek,

Am 07.05.19 um 14:03 schrieb Marek Szyprowski:
> Hi All,
> 
> On 2019-05-07 11:17, Marek Szyprowski wrote:
>> Hi Markus,
>>
>> On 2019-05-07 10:12, Markus Reichl wrote:
>>> Hi Marek,
>>>
>>> your patch did not help on stable v5.1
>>>
>>> [    3.255963] samsung-usb2-phy 125b0000.exynos-usbphy: 
>>> 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
>>> [    4.044547] usbcore: registered new interface driver smsc95xx
>>> [    4.112261] usb usb1: New USB device found, idVendor=1d6b, 
>>> idProduct=0002, bcdDevice= 5.01
>>> [    4.120363] usb usb1: New USB device strings: Mfr=3, Product=2, 
>>> SerialNumber=1
>>> [    4.127560] usb usb1: Product: EHCI Host Controller
>>> [    4.132415] usb usb1: Manufacturer: Linux 
>>> 5.1.0-00005-geb4efae48eb5 ehci_hcd
>>> [    4.139446] usb usb1: SerialNumber: 12580000.ehci
>>> [    4.183056] usb3503 0-0008: switched to HUB mode
>>> [    4.183121] usb3503 0-0008: usb3503_probe: probed in hub mode
>>> [    4.488344] usb 1-2: new high-speed USB device number 2 using 
>>> exynos-ehci
>>> [    4.675605] usb 1-2: New USB device found, idVendor=0424, 
>>> idProduct=3503, bcdDevice=a1.a0
>>> [    4.678166] usb 1-2: New USB device strings: Mfr=0, Product=0, 
>>> SerialNumber=0
>>> [    4.686140] usb 1-2: skipping disabled interface 0
>>>
>>> root@odroid-x2:~# lsusb
>>> Bus 001 Device 002: ID 0424:3503 Standard Microsystems Corp.
>>> Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
>>
>> This patch fixes the issue introduced by "usb: dwc2: gadget: Replace 
>> phyif with phy_utmi_width" commit, which is queued only to linux-next 
>> so far. Stable v5.1 doesn't include it, so the fix doesn't change 
>> anything on v5.1.
>>
>> I've checked and OdroidU3 works fine with v5.1 release, but X2 fails 
>> to detect USB devices. I will investigate this in a few minutes...
> 
> 
> Broken USB on X2 is caused by commit 
> 01fdf179f4b064d4c9d30b39aba178caf32649f4 ("usb: core: skip interfaces 
> disabled in devicetree").
> 
> I looks that the mentioned commit conflicts with the Exynos EHCI and 
> OHCI bindings and the way the PHY ports are defined for those drivers. 
> It worked on U3 only by the pure coincidence. This is probably a 
> "minimal" fix for this issue:

Thanks Marek, below fix enables USB on Odroid-X2 with stable v5.1.

> 
> diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
> index 82239f27c4cc..cd455c4add25 100644
> --- a/drivers/usb/core/message.c
> +++ b/drivers/usb/core/message.c
> @@ -2007,6 +2007,7 @@ int usb_set_configuration(struct usb_device *dev, 
> int configuration)
>                  struct usb_interface *intf = cp->interface[i];
> 
>                  if (intf->dev.of_node &&
> +                   of_device_is_compatible(intf->dev.of_node, NULL) &&
>                      !of_device_is_available(intf->dev.of_node)) {
>                          dev_info(&dev->dev, "skipping disabled 
> interface %d\n",
> intf->cur_altsetting->desc.bInterfaceNumber);
> 
> I will try to describe the problem in details and discuss it on the usb 
> mailing list.
> 
> Best regards
> 

Gruß,
-- 
Markus Reichl


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Re: [PATCH] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs

[Krzysztof Kozlowski]

On Mon, 6 May 2019 at 15:00, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
> Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
> host side of the shared USB2 PHY doesn't work.
>
> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [BUG BISECT] USB on Exynos4412 fails after usb: dwc2: gadget: Replace phyif with phy_utmi_width

[Minas Harutyunyan]

Hi Krzysztof,

On 5/4/2019 12:50 AM, Krzysztof Kozlowski wrote:
> Hi,
> 
> Bisect pointed commit 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif
> with phy_utmi_width") as reason for failures of USB on Exynos4412,
> Odroid U3 board (ARMv7, exynos_defconfig, TFTP boot with nfsroot from
> NFSv4):
> 
> [    4.333996] usb 1-2: new high-speed USB device number 3 using exynos-ehci
> [    4.503942] usb 1-2: device descriptor read/64, error -71
> [    4.793970] usb 1-2: device descriptor read/64, error -71
> [    4.914748] usb usb1-port2: attempt power cycle
> [    6.224267] usb 1-3: new high-speed USB device number 5 using exynos-ehci
> [    6.393983] usb 1-3: device descriptor read/64, error -71
> [    6.684243] usb 1-3: device descriptor read/64, error -71
> [    6.954259] usb 1-3: new high-speed USB device number 6 using exynos-ehci
> [    7.123980] usb 1-3: device descriptor read/64, error -71
> [    7.413969] usb 1-3: device descriptor read/64, error -71
> [    7.534778] usb usb1-port3: attempt power cycle
> 
> The boot failure is effect of lack of network adapter (USB, smsc95xx).
> Expected:
> [    4.285831] usb 1-3: New USB device found, idVendor=0424, idProduct=3503, bcdDevice=a1.a0
> [    4.288986] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> [    4.299596] hub 1-3:1.0: USB hub found
> [    4.300027] hub 1-3:1.0: 3 ports detected
> [    5.895541] smsc95xx 1-2:1.0 eth0: link up, 100Mbps, full-duplex, lpa 0xCDE1
> 
> Full kernel log is here:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__krzk.eu_-23_builders_25_builds_1330_steps_14_logs_serial0&d=DwIBaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=6z9Al9FrHR_ZqbbtSAsD16pvOL2S3XHxQnSzq8kusyI&m=OiD-VOiMNPgl24seQpn5JKZq7f85A4LNzaz8zX0YrKs&s=WBsxDt_1PXo9t9AxxJkUTTLE6zx_UDc7ac_U3EydCzI&e=
> https://urldefense.proofpoint.com/v2/url?u=https-3A__krzk.eu_-23_builders_25_builds_1330&d=DwIBaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=6z9Al9FrHR_ZqbbtSAsD16pvOL2S3XHxQnSzq8kusyI&m=OiD-VOiMNPgl24seQpn5JKZq7f85A4LNzaz8zX0YrKs&s=Lxk4ZiitEFaod88HTY0hthrdRy_TtktU53P6UDtaCoE&e=
> 
> Let me know if you need any more details.
> 
> Best regards,
> Krzysztof
> 
> 

But fail seen on ehci driver not dwc2.

Thanks,
Minas

Re: [BUG BISECT] USB on Exynos4412 fails after usb: dwc2: gadget: Replace phyif with phy_utmi_width

[Marek Szyprowski]

Hi Minas,

On 2019-05-07 08:21, Minas Harutyunyan wrote:
> Hi Krzysztof,
>
> On 5/4/2019 12:50 AM, Krzysztof Kozlowski wrote:
>> Hi,
>>
>> Bisect pointed commit 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif
>> with phy_utmi_width") as reason for failures of USB on Exynos4412,
>> Odroid U3 board (ARMv7, exynos_defconfig, TFTP boot with nfsroot from
>> NFSv4):
>>
>> [    4.333996] usb 1-2: new high-speed USB device number 3 using 
>> exynos-ehci
>> [    4.503942] usb 1-2: device descriptor read/64, error -71
>> [    4.793970] usb 1-2: device descriptor read/64, error -71
>> [    4.914748] usb usb1-port2: attempt power cycle
>> [    6.224267] usb 1-3: new high-speed USB device number 5 using 
>> exynos-ehci
>> [    6.393983] usb 1-3: device descriptor read/64, error -71
>> [    6.684243] usb 1-3: device descriptor read/64, error -71
>> [    6.954259] usb 1-3: new high-speed USB device number 6 using 
>> exynos-ehci
>> [    7.123980] usb 1-3: device descriptor read/64, error -71
>> [    7.413969] usb 1-3: device descriptor read/64, error -71
>> [    7.534778] usb usb1-port3: attempt power cycle
>>
>> The boot failure is effect of lack of network adapter (USB, smsc95xx).
>> Expected:
>> [    4.285831] usb 1-3: New USB device found, idVendor=0424, 
>> idProduct=3503, bcdDevice=a1.a0
>> [    4.288986] usb 1-3: New USB device strings: Mfr=0, Product=0, 
>> SerialNumber=0
>> [    4.299596] hub 1-3:1.0: USB hub found
>> [    4.300027] hub 1-3:1.0: 3 ports detected
>> [    5.895541] smsc95xx 1-2:1.0 eth0: link up, 100Mbps, full-duplex, 
>> lpa 0xCDE1
>>
>> Full kernel log is here:
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__krzk.eu_-23_builders_25_builds_1330_steps_14_logs_serial0&d=DwIBaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=6z9Al9FrHR_ZqbbtSAsD16pvOL2S3XHxQnSzq8kusyI&m=OiD-VOiMNPgl24seQpn5JKZq7f85A4LNzaz8zX0YrKs&s=WBsxDt_1PXo9t9AxxJkUTTLE6zx_UDc7ac_U3EydCzI&e= 
>>
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__krzk.eu_-23_builders_25_builds_1330&d=DwIBaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=6z9Al9FrHR_ZqbbtSAsD16pvOL2S3XHxQnSzq8kusyI&m=OiD-VOiMNPgl24seQpn5JKZq7f85A4LNzaz8zX0YrKs&s=Lxk4ZiitEFaod88HTY0hthrdRy_TtktU53P6UDtaCoE&e= 
>>
>>
>> Let me know if you need any more details.
>>
>> Best regards,
>> Krzysztof
>>
>>
>
> But fail seen on ehci driver not dwc2.

Right, but dwc2 and ehci share common USB2 PHY on Exynos4 SoCs, although 
they use different ports of it.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH] usb: dwc2: Use generic PHY width in params setup

[Jules Maselbas]

Hi,

The patch 'usb: dwc2: gadget: Replace phyif with phy_utmi_width'
changed a little the "behavior" of the platform lowlevel hw init.

As setting the params.utmi_phy_width at that time is pointless,
see the attached patch for detailed information.

I think that's why the USB on Exynos4412 fails, and why adding
the width information in s3c6400_params fixes this issue.

However I don't have the hardware to test if this patch resolve
the issue on Exynos4412, any tester would more than welcome.

Cheers

--
Jules

[PATCH] usb: dwc2: Use generic PHY width in params setup

[Jules Maselbas]

Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since
it's value will be overwritten by dwc2_init_params().

This change make sure to take in account the generic PHY width information
during parmas initialization, done in dwc2_set_param_phy_utmi_width().

By doing so, the phy_utmi_width params can still be overridden by
devicetree specific params and will also be checked against hardware
capabilities.

Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
---
 drivers/usb/dwc2/params.c   | 9 +++++++++
 drivers/usb/dwc2/platform.c | 9 ---------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 6900eea57526..5949262ff669 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 	val = (hsotg->hw_params.utmi_phy_data_width ==
 	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 
+	if (hsotg->phy) {
+		/*
+		 * If using the generic PHY framework, check if the PHY bus
+		 * width is 8-bit and set the phyif appropriately.
+		 */
+		if (phy_get_bus_width(hsotg->phy) == 8)
+			val = 8;
+	}
+
 	hsotg->params.phy_utmi_width = val;
 }
 
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index d10a7f8daec3..e98d7812da2d 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 
 	hsotg->plat = dev_get_platdata(hsotg->dev);
 
-	if (hsotg->phy) {
-		/*
-		 * If using the generic PHY framework, check if the PHY bus
-		 * width is 8-bit and set the phyif appropriately.
-		 */
-		if (phy_get_bus_width(hsotg->phy) == 8)
-			hsotg->params.phy_utmi_width = 8;
-	}
-
 	/* Clock */
 	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
-- 
2.21.0.196.g041f5ea

Re: [PATCH] usb: dwc2: Use generic PHY width in params setup

[Marek Szyprowski]

Hi Jules,

On 2019-05-07 12:08, Jules Maselbas wrote:
> Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since
> it's value will be overwritten by dwc2_init_params().
>
> This change make sure to take in account the generic PHY width information
> during parmas initialization, done in dwc2_set_param_phy_utmi_width().
>
> By doing so, the phy_utmi_width params can still be overridden by
> devicetree specific params and will also be checked against hardware
> capabilities.
>
> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>

Right, this fixes the issue spotten on Exynos4412 SoCs.

Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>

IMHO it would also make sense to add:

Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")

> ---
>   drivers/usb/dwc2/params.c   | 9 +++++++++
>   drivers/usb/dwc2/platform.c | 9 ---------
>   2 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..5949262ff669 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
>   	val = (hsotg->hw_params.utmi_phy_data_width ==
>   	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
>   
> +	if (hsotg->phy) {
> +		/*
> +		 * If using the generic PHY framework, check if the PHY bus
> +		 * width is 8-bit and set the phyif appropriately.
> +		 */
> +		if (phy_get_bus_width(hsotg->phy) == 8)
> +			val = 8;
> +	}
> +
>   	hsotg->params.phy_utmi_width = val;
>   }
>   
> diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
> index d10a7f8daec3..e98d7812da2d 100644
> --- a/drivers/usb/dwc2/platform.c
> +++ b/drivers/usb/dwc2/platform.c
> @@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
>   
>   	hsotg->plat = dev_get_platdata(hsotg->dev);
>   
> -	if (hsotg->phy) {
> -		/*
> -		 * If using the generic PHY framework, check if the PHY bus
> -		 * width is 8-bit and set the phyif appropriately.
> -		 */
> -		if (phy_get_bus_width(hsotg->phy) == 8)
> -			hsotg->params.phy_utmi_width = 8;
> -	}
> -
>   	/* Clock */
>   	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
>   	if (IS_ERR(hsotg->clk)) {

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH v2] usb: dwc2: Use generic PHY width in params setup

[Jules Maselbas]

Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since
it's value will be overwritten by dwc2_init_params().

This change make sure to take in account the generic PHY width information
during paraminitialisation, done in dwc2_set_param_phy_utmi_width().

By doing so, the phy_utmi_width params can still be overrided by
devicetree specific params and will also be checked against hardware
capabilities.

Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
---
v2: Fix typo in commit message. Add Fixes and Tested-by tags.
---
 drivers/usb/dwc2/params.c   | 9 +++++++++
 drivers/usb/dwc2/platform.c | 9 ---------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 6900eea57526..5949262ff669 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 	val = (hsotg->hw_params.utmi_phy_data_width ==
 	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 
+	if (hsotg->phy) {
+		/*
+		 * If using the generic PHY framework, check if the PHY bus
+		 * width is 8-bit and set the phyif appropriately.
+		 */
+		if (phy_get_bus_width(hsotg->phy) == 8)
+			val = 8;
+	}
+
 	hsotg->params.phy_utmi_width = val;
 }
 
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index d10a7f8daec3..e98d7812da2d 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 
 	hsotg->plat = dev_get_platdata(hsotg->dev);
 
-	if (hsotg->phy) {
-		/*
-		 * If using the generic PHY framework, check if the PHY bus
-		 * width is 8-bit and set the phyif appropriately.
-		 */
-		if (phy_get_bus_width(hsotg->phy) == 8)
-			hsotg->params.phy_utmi_width = 8;
-	}
-
 	/* Clock */
 	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
-- 
2.21.0.196.g041f5ea

Re: [PATCH v2] usb: dwc2: Use generic PHY width in params setup

[Jules Maselbas]

Hi Minas,

This is a reminder in case you missed this patch.

Kind regards,
Jules

On Thu, May 09, 2019 at 11:15:28AM +0200, Jules Maselbas wrote:
> Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since
> it's value will be overwritten by dwc2_init_params().
> 
> This change make sure to take in account the generic PHY width information
> during paraminitialisation, done in dwc2_set_param_phy_utmi_width().
> 
> By doing so, the phy_utmi_width params can still be overrided by
> devicetree specific params and will also be checked against hardware
> capabilities.
> 
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
> ---
> v2: Fix typo in commit message. Add Fixes and Tested-by tags.
> ---
>  drivers/usb/dwc2/params.c   | 9 +++++++++
>  drivers/usb/dwc2/platform.c | 9 ---------
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..5949262ff669 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
>  	val = (hsotg->hw_params.utmi_phy_data_width ==
>  	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
>  
> +	if (hsotg->phy) {
> +		/*
> +		 * If using the generic PHY framework, check if the PHY bus
> +		 * width is 8-bit and set the phyif appropriately.
> +		 */
> +		if (phy_get_bus_width(hsotg->phy) == 8)
> +			val = 8;
> +	}
> +
>  	hsotg->params.phy_utmi_width = val;
>  }
>  
> diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
> index d10a7f8daec3..e98d7812da2d 100644
> --- a/drivers/usb/dwc2/platform.c
> +++ b/drivers/usb/dwc2/platform.c
> @@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
>  
>  	hsotg->plat = dev_get_platdata(hsotg->dev);
>  
> -	if (hsotg->phy) {
> -		/*
> -		 * If using the generic PHY framework, check if the PHY bus
> -		 * width is 8-bit and set the phyif appropriately.
> -		 */
> -		if (phy_get_bus_width(hsotg->phy) == 8)
> -			hsotg->params.phy_utmi_width = 8;
> -	}
> -
>  	/* Clock */
>  	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
>  	if (IS_ERR(hsotg->clk)) {
> -- 
> 2.21.0.196.g041f5ea
> 

Re: [PATCH v2] usb: dwc2: Use generic PHY width in params setup

[Minas Harutyunyan]

On 5/9/2019 1:16 PM, Jules Maselbas wrote:
> Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since
> it's value will be overwritten by dwc2_init_params().
> 
> This change make sure to take in account the generic PHY width information
> during paraminitialisation, done in dwc2_set_param_phy_utmi_width().
> 
> By doing so, the phy_utmi_width params can still be overrided by
> devicetree specific params and will also be checked against hardware
> capabilities.
> 
> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>

Acked-by: Minas Harutyunyan <hminas@synopsys.com>

> ---
> v2: Fix typo in commit message. Add Fixes and Tested-by tags.
> ---
>   drivers/usb/dwc2/params.c   | 9 +++++++++
>   drivers/usb/dwc2/platform.c | 9 ---------
>   2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 6900eea57526..5949262ff669 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
>   	val = (hsotg->hw_params.utmi_phy_data_width ==
>   	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
>   
> +	if (hsotg->phy) {
> +		/*
> +		 * If using the generic PHY framework, check if the PHY bus
> +		 * width is 8-bit and set the phyif appropriately.
> +		 */
> +		if (phy_get_bus_width(hsotg->phy) == 8)
> +			val = 8;
> +	}
> +
>   	hsotg->params.phy_utmi_width = val;
>   }
>   
> diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
> index d10a7f8daec3..e98d7812da2d 100644
> --- a/drivers/usb/dwc2/platform.c
> +++ b/drivers/usb/dwc2/platform.c
> @@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
>   
>   	hsotg->plat = dev_get_platdata(hsotg->dev);
>   
> -	if (hsotg->phy) {
> -		/*
> -		 * If using the generic PHY framework, check if the PHY bus
> -		 * width is 8-bit and set the phyif appropriately.
> -		 */
> -		if (phy_get_bus_width(hsotg->phy) == 8)
> -			hsotg->params.phy_utmi_width = 8;
> -	}
> -
>   	/* Clock */
>   	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
>   	if (IS_ERR(hsotg->clk)) {
> 

Re: [PATCH v2] usb: dwc2: Use generic PHY width in params setup

[Marek Szyprowski]

Hi All,

On 2019-05-31 14:44, Minas Harutyunyan wrote:
> On 5/9/2019 1:16 PM, Jules Maselbas wrote:
>> Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless 
>> since
>> it's value will be overwritten by dwc2_init_params().
>>
>> This change make sure to take in account the generic PHY width 
>> information
>> during paraminitialisation, done in dwc2_set_param_phy_utmi_width().
>>
>> By doing so, the phy_utmi_width params can still be overrided by
>> devicetree specific params and will also be checked against hardware
>> capabilities.
>>
>> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with 
>> phy_utmi_width")
>> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
>
> Acked-by: Minas Harutyunyan <hminas@synopsys.com>

Gentle reminder, Felipe, could you take this to the fixes for v5.2?

>> ---
>> v2: Fix typo in commit message. Add Fixes and Tested-by tags.
>> ---
>>   drivers/usb/dwc2/params.c   | 9 +++++++++
>>   drivers/usb/dwc2/platform.c | 9 ---------
>>   2 files changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
>> index 6900eea57526..5949262ff669 100644
>> --- a/drivers/usb/dwc2/params.c
>> +++ b/drivers/usb/dwc2/params.c
>> @@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct 
>> dwc2_hsotg *hsotg)
>>       val = (hsotg->hw_params.utmi_phy_data_width ==
>>              GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
>>   +    if (hsotg->phy) {
>> +        /*
>> +         * If using the generic PHY framework, check if the PHY bus
>> +         * width is 8-bit and set the phyif appropriately.
>> +         */
>> +        if (phy_get_bus_width(hsotg->phy) == 8)
>> +            val = 8;
>> +    }
>> +
>>       hsotg->params.phy_utmi_width = val;
>>   }
>>   diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
>> index d10a7f8daec3..e98d7812da2d 100644
>> --- a/drivers/usb/dwc2/platform.c
>> +++ b/drivers/usb/dwc2/platform.c
>> @@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct 
>> dwc2_hsotg *hsotg)
>>         hsotg->plat = dev_get_platdata(hsotg->dev);
>>   -    if (hsotg->phy) {
>> -        /*
>> -         * If using the generic PHY framework, check if the PHY bus
>> -         * width is 8-bit and set the phyif appropriately.
>> -         */
>> -        if (phy_get_bus_width(hsotg->phy) == 8)
>> -            hsotg->params.phy_utmi_width = 8;
>> -    }
>> -
>>       /* Clock */
>>       hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
>>       if (IS_ERR(hsotg->clk)) {
>>
>
>
>
Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2] usb: dwc2: Use generic PHY width in params setup

[Felipe Balbi]

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Hi,

Marek Szyprowski <m.szyprowski@samsung.com> writes:
> Hi All,
>
> On 2019-05-31 14:44, Minas Harutyunyan wrote:
>> On 5/9/2019 1:16 PM, Jules Maselbas wrote:
>>> Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless 
>>> since
>>> it's value will be overwritten by dwc2_init_params().
>>>
>>> This change make sure to take in account the generic PHY width 
>>> information
>>> during paraminitialisation, done in dwc2_set_param_phy_utmi_width().
>>>
>>> By doing so, the phy_utmi_width params can still be overrided by
>>> devicetree specific params and will also be checked against hardware
>>> capabilities.
>>>
>>> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with 
>>> phy_utmi_width")
>>> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
>>
>> Acked-by: Minas Harutyunyan <hminas@synopsys.com>
>
> Gentle reminder, Felipe, could you take this to the fixes for v5.2?

darn it, I applied for 'next'. I'll remove from that branch and place it
in fixes. Pull request, hopefully, tomorrow.

-- 
balbi

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