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Mon, 2 Aug 2021 18:15:22 +0000 Subject: Re: [PATCH 2/4] thunderbolt: Handle INTR when Disable ISR auto clear bit set To: Mika Westerberg , Sanjay R Mehta Cc: andreas.noever@gmail.com, michael.jamet@intel.com, bhelgaas@google.com, YehezkelShB@gmail.com, Basavaraj.Natikar@amd.com, linux-usb@vger.kernel.org, linux-pci@vger.kernel.org References: <1627909100-83338-1-git-send-email-Sanju.Mehta@amd.com> <1627909100-83338-3-git-send-email-Sanju.Mehta@amd.com> From: Sanjay R Mehta Message-ID: Date: Mon, 2 Aug 2021 23:45:07 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PN1PR0101CA0053.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::15) To DM4PR12MB5103.namprd12.prod.outlook.com (2603:10b6:5:392::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [172.31.32.35] (165.204.159.242) by PN1PR0101CA0053.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.18 via Frontend Transport; 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Hence handling it by setting >> the "Interrupt status clear" register to clear the >> corresponding Tx/Rx ring interrupt. > > I think REG_DMA_MISC_INT_AUTO_CLEAR which is bit 2 in that register is > actually Intel specific and not the same as in the USB4 spec bit 17. I > guess the AMD controller works fine as is if this bit (2) is not set? If > that's the case we can simply limit this behavior for Intel controllers. > Yes, you are right Mika. With bit 17 it's working for us and we didn't wanted to break Intel's functionality , hence we added this change which works for both :). Yes, as you suggested, we can limit this to Intel controllers. Will send the changes accordingly. Thanks, Sanjay >> >> Signed-off-by: Basavaraj Natikar >> Signed-off-by: Sanjay R Mehta >> --- >> drivers/thunderbolt/nhi.c | 26 +++++++++++++++++++++++++- >> include/linux/thunderbolt.h | 1 + >> 2 files changed, 26 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c >> index d7d9c4b..63bbabf 100644 >> --- a/drivers/thunderbolt/nhi.c >> +++ b/drivers/thunderbolt/nhi.c >> @@ -74,7 +74,11 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) >> if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { >> misc |= REG_DMA_MISC_INT_AUTO_CLEAR; >> iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); >> - } >> + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); >> + if (misc & REG_DMA_MISC_INT_AUTO_CLEAR) >> + ring->nhi->is_intr_autoclr = true; >> + } else >> + ring->nhi->is_intr_autoclr = true; >> >> ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; >> step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; >> @@ -377,11 +381,31 @@ void tb_ring_poll_complete(struct tb_ring *ring) >> } >> EXPORT_SYMBOL_GPL(tb_ring_poll_complete); >> >> +static void check_and_clear_intr_status(struct tb_ring *ring, int int_pos) >> +{ >> + u32 value; >> + >> + if (!ring->nhi->is_intr_autoclr) { >> + value = ioread32(ring->nhi->iobase >> + + REG_RING_NOTIFY_BASE >> + + 4 * (int_pos / 32)); >> + iowrite32(value, ring->nhi->iobase >> + + (REG_RING_NOTIFY_BASE + 8) >> + + 4 * (int_pos / 32)); >> + } >> +} >> + >> static irqreturn_t ring_msix(int irq, void *data) >> { >> struct tb_ring *ring = data; >> >> spin_lock(&ring->nhi->lock); >> + >> + if (ring->is_tx) >> + check_and_clear_intr_status(ring, 0); >> + else >> + check_and_clear_intr_status(ring, ring->nhi->hop_count); >> + >> spin_lock(&ring->lock); >> __ring_interrupt(ring); >> spin_unlock(&ring->lock); >> diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h >> index e7c96c3..bbe7c7e 100644 >> --- a/include/linux/thunderbolt.h >> +++ b/include/linux/thunderbolt.h >> @@ -478,6 +478,7 @@ struct tb_nhi { >> struct tb_ring **rx_rings; >> struct ida msix_ida; >> bool going_away; >> + bool is_intr_autoclr; >> struct work_struct interrupt_work; >> u32 hop_count; >> }; >> -- >> 2.7.4