From: Guenter Roeck <linux@roeck-us.net>
To: Jiaxin Yu <jiaxin.yu@mediatek.com>,
yong.liang@mediatek.com, wim@linux-watchdog.org,
p.zabel@pengutronix.de, matthias.bgg@gmail.com,
linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
chang-an.chen@mediatek.com, freddy.hsin@mediatek.com
Cc: yingjoe.chen@mediatek.com, sboyd@kernel.org
Subject: Re: [PATCH v9 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells
Date: Sun, 5 Jan 2020 18:22:35 -0800 [thread overview]
Message-ID: <04f9dbd7-4d96-cdbf-0bb2-9c34e8d84dc9@roeck-us.net> (raw)
In-Reply-To: <1578241301-14618-2-git-send-email-jiaxin.yu@mediatek.com>
On 1/5/20 8:21 AM, Jiaxin Yu wrote:
> Add #reset-cells property and update example
>
> Signed-off-by: yong.liang <yong.liang@mediatek.com>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++
> .../reset-controller/mt8183-resets.h | 17 ++++++++++++++
> 2 files changed, 39 insertions(+)
> create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h
>
Repeating Rob's question from v8: What happened to the bindings document ?
Guenter
> diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h
> new file mode 100644
> index 000000000000..9e7ee762f076
> --- /dev/null
> +++ b/include/dt-bindings/reset-controller/mt2712-resets.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Yong Liang <yong.liang@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712
> +
> +#define MT2712_TOPRGU_INFRA_SW_RST 0
> +#define MT2712_TOPRGU_MM_SW_RST 1
> +#define MT2712_TOPRGU_MFG_SW_RST 2
> +#define MT2712_TOPRGU_VENC_SW_RST 3
> +#define MT2712_TOPRGU_VDEC_SW_RST 4
> +#define MT2712_TOPRGU_IMG_SW_RST 5
> +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8
> +#define MT2712_TOPRGU_USB_SW_RST 9
> +#define MT2712_TOPRGU_APMIXED_SW_RST 10
> +
> +#define MT2712_TOPRGU_SW_RST_NUM 11
> +
> +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */
> diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h
> index 8804e34ebdd4..a1bbd41e0d12 100644
> --- a/include/dt-bindings/reset-controller/mt8183-resets.h
> +++ b/include/dt-bindings/reset-controller/mt8183-resets.h
> @@ -78,4 +78,21 @@
> #define MT8183_INFRACFG_AO_I2C7_SW_RST 126
> #define MT8183_INFRACFG_AO_I2C8_SW_RST 127
>
> +#define MT8183_INFRACFG_SW_RST_NUM 128
> +
> +#define MT8183_TOPRGU_MM_SW_RST 1
> +#define MT8183_TOPRGU_MFG_SW_RST 2
> +#define MT8183_TOPRGU_VENC_SW_RST 3
> +#define MT8183_TOPRGU_VDEC_SW_RST 4
> +#define MT8183_TOPRGU_IMG_SW_RST 5
> +#define MT8183_TOPRGU_MD_SW_RST 7
> +#define MT8183_TOPRGU_CONN_SW_RST 9
> +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12
> +#define MT8183_TOPRGU_IPU0_SW_RST 14
> +#define MT8183_TOPRGU_IPU1_SW_RST 15
> +#define MT8183_TOPRGU_AUDIO_SW_RST 17
> +#define MT8183_TOPRGU_CAMSYS_SW_RST 18
> +
> +#define MT8183_TOPRGU_SW_RST_NUM 19
> +
> #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
>
next prev parent reply other threads:[~2020-01-06 2:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-05 16:21 [PATCH v9 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu
2020-01-05 16:21 ` [PATCH v9 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu
2020-01-06 2:22 ` Guenter Roeck [this message]
2020-01-05 16:21 ` [PATCH v9 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu
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