From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-path: Received: from relmlor4.renesas.com ([210.160.252.174]:19507 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726683AbeIGGBS (ORCPT ); Fri, 7 Sep 2018 02:01:18 -0400 From: Chris Brandt To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Mark Rutland , Geert Uytterhoeven Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Chris Brandt Subject: [PATCH v3 1/2] watchdog: rza_wdt: Support longer timeouts Date: Thu, 6 Sep 2018 20:22:42 -0500 Message-Id: <20180907012243.86603-2-chris.brandt@renesas.com> In-Reply-To: <20180907012243.86603-1-chris.brandt@renesas.com> References: <20180907012243.86603-1-chris.brandt@renesas.com> Sender: linux-watchdog-owner@vger.kernel.org List-Id: linux-watchdog@vger.kernel.org The RZ/A2 watchdog timer extends the clock source options in order to allow for longer timeouts. Signed-off-by: Chris Brandt --- v3: * Removed + 1 from DIV_ROUND_UP line * resetting to 0 if time to big did not make as much sense are resetting to 256 v2: * use DIV_ROUND_UP * use %u for pr_debug * use of_match data to determine the size of CKS register --- drivers/watchdog/rza_wdt.c | 81 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 18 deletions(-) diff --git a/drivers/watchdog/rza_wdt.c b/drivers/watchdog/rza_wdt.c index e618218d2374..64a733492b96 100644 --- a/drivers/watchdog/rza_wdt.c +++ b/drivers/watchdog/rza_wdt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -34,12 +35,40 @@ #define WRCSR_RSTE BIT(6) #define WRCSR_CLEAR_WOVF 0xA500 /* special value */ +#define CKS_3BIT 0x7 +#define CKS_4BIT 0xF + struct rza_wdt { struct watchdog_device wdev; void __iomem *base; struct clk *clk; + u8 count; + u8 cks; + u8 timeout; }; +static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout) +{ + unsigned long rate = clk_get_rate(priv->clk); + unsigned int ticks; + + if (priv->cks == CKS_4BIT) { + ticks = DIV_ROUND_UP((timeout * rate), 4194304); + if (ticks > 256) + ticks = 256; + + priv->count = 256 - ticks; + } else { + /* Start timer with longest timeout */ + priv->count = 0; + } + + priv->timeout = timeout; + + pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__, + timeout, priv->count); +} + static int rza_wdt_start(struct watchdog_device *wdev) { struct rza_wdt *priv = watchdog_get_drvdata(wdev); @@ -51,13 +80,12 @@ static int rza_wdt_start(struct watchdog_device *wdev) readb(priv->base + WRCSR); writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); - /* - * Start timer with slowest clock source and reset option enabled. - */ + rza_wdt_calc_timeout(priv, wdev->timeout); + writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); - writew(WTCNT_MAGIC | 0, priv->base + WTCNT); - writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | WTSCR_CKS(7), - priv->base + WTCSR); + writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); + writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | + WTSCR_CKS(priv->cks), priv->base + WTCSR); return 0; } @@ -75,7 +103,12 @@ static int rza_wdt_ping(struct watchdog_device *wdev) { struct rza_wdt *priv = watchdog_get_drvdata(wdev); - writew(WTCNT_MAGIC | 0, priv->base + WTCNT); + if (priv->timeout != wdev->timeout) + rza_wdt_calc_timeout(priv, wdev->timeout); + + writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); + + pr_debug("%s: timeout = %u\n", __func__, wdev->timeout); return 0; } @@ -150,20 +183,31 @@ static int rza_wdt_probe(struct platform_device *pdev) return -ENOENT; } - /* Assume slowest clock rate possible (CKS=7) */ - rate /= 16384; - priv->wdev.info = &rza_wdt_ident, priv->wdev.ops = &rza_wdt_ops, priv->wdev.parent = &pdev->dev; - /* - * Since the max possible timeout of our 8-bit count register is less - * than a second, we must use max_hw_heartbeat_ms. - */ - priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate; - dev_dbg(&pdev->dev, "max hw timeout of %dms\n", - priv->wdev.max_hw_heartbeat_ms); + priv->cks = (unsigned int)of_device_get_match_data(&pdev->dev); + if (priv->cks == CKS_4BIT) { + /* Assume slowest clock rate possible (CKS=0xF) */ + priv->wdev.max_timeout = (4194304 * U8_MAX) / rate; + + } else if (priv->cks == CKS_3BIT) { + /* Assume slowest clock rate possible (CKS=7) */ + rate /= 16384; + + /* + * Since the max possible timeout of our 8-bit count + * register is less than a second, we must use + * max_hw_heartbeat_ms. + */ + priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate; + dev_dbg(&pdev->dev, "max hw timeout of %dms\n", + priv->wdev.max_hw_heartbeat_ms); + } else { + dev_err(&pdev->dev, "invalid CKS value (%u)\n", priv->cks); + return -EINVAL; + } priv->wdev.min_timeout = 1; priv->wdev.timeout = DEFAULT_TIMEOUT; @@ -179,7 +223,8 @@ static int rza_wdt_probe(struct platform_device *pdev) } static const struct of_device_id rza_wdt_of_match[] = { - { .compatible = "renesas,rza-wdt", }, + { .compatible = "renesas,r7s9210-wdt", .data = (void *)CKS_4BIT, }, + { .compatible = "renesas,rza-wdt", .data = (void *)CKS_3BIT, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rza_wdt_of_match); -- 2.16.1