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From: Simon Horman <horms@verge.net.au>
To: Guenter Roeck <linux@roeck-us.net>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	wim@linux-watchdog.org, linux-watchdog@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v3] watchdog: renesas_wdt: Add a few cycles delay
Date: Thu, 13 Jun 2019 11:28:56 +0200
Message-ID: <20190613092855.hqbsgzil4xl6owyz@verge.net.au> (raw)
In-Reply-To: <20190607174411.GA15497@roeck-us.net>

On Fri, Jun 07, 2019 at 10:44:11AM -0700, Guenter Roeck wrote:
> [Note: I updated the subject to "PATCH v3"]
> 
> On Wed, Jun 05, 2019 at 02:04:00PM +0900, Yoshihiro Shimoda wrote:
> > According to the hardware manual of R-Car Gen2 and Gen3,
> > software should wait a few RLCK cycles as following:
> >  - Delay 2 cycles before setting watchdog counter.
> >  - Delay 3 cycles before disabling module clock.
> > 
> > So, this patch adds such delays.
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> 
> Reviewed-by: Guenter Roeck <linux@roeck-us.net>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>


      reply index

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-05  5:04 [PATCH] " Yoshihiro Shimoda
2019-06-05  5:21 ` Yoshihiro Shimoda
2019-06-07 17:44 ` [PATCH v3] " Guenter Roeck
2019-06-13  9:28   ` Simon Horman [this message]

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