[PATCH 0/7] Add RZ/G2N MSIOF/RWDT/PCIEC support

[PATCH 0/7] Add RZ/G2N MSIOF/RWDT/PCIEC support

[Fabrizio Castro]

Dear All,

this series adds MSDIF/RWDT/PCIEC support to the HiHope RZ/G2N.

This series depends on the following series and patches:
* https://patchwork.kernel.org/cover/11166155/
* https://patchwork.kernel.org/cover/11157129/
* https://patchwork.kernel.org/cover/11158259/
* https://patchwork.kernel.org/patch/11166327/
* https://patchwork.kernel.org/cover/11171325/
* https://patchwork.kernel.org/patch/11162283/

Thanks,
Fab

Fabrizio Castro (7):
  dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support
  dt-bindings: spi: sh-msiof: Add r8a774b1 support
  dt-bindings: PCI: rcar: Add device tree support for r8a774b1
  arm64: dts: renesas: r8a774b1: Add RWDT node
  arm64: dts: renesas: r8a774b1: Add all MSIOF nodes
  arm64: dts: renesas: r8a774b1: Add PCIe device nodes
  arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide
    about pciec1

 Documentation/devicetree/bindings/pci/rcar-pci.txt |   1 +
 .../devicetree/bindings/spi/renesas,sh-msiof.yaml  |   1 +
 .../devicetree/bindings/watchdog/renesas,wdt.txt   |   1 +
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi    |   4 -
 .../boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts  |   4 +
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi          | 111 ++++++++++++++++++++-
 6 files changed, 115 insertions(+), 7 deletions(-)

-- 
2.7.4

[PATCH 1/7] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

[Fabrizio Castro]

RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
with R-Car Gen3, therefore add the relevant documentation.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
index 9f365c1..a5bf04d 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -10,6 +10,7 @@ Required properties:
 		 - "renesas,r8a7745-wdt" (RZ/G1E)
 		 - "renesas,r8a77470-wdt" (RZ/G1C)
 		 - "renesas,r8a774a1-wdt" (RZ/G2M)
+		 - "renesas,r8a774b1-wdt" (RZ/G2N)
 		 - "renesas,r8a774c0-wdt" (RZ/G2E)
 	         - "renesas,r8a7790-wdt" (R-Car H2)
 	         - "renesas,r8a7791-wdt" (R-Car M2-W)
-- 
2.7.4

Re: [PATCH 1/7] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

[Guenter Roeck]

On 10/4/19 1:35 AM, Fabrizio Castro wrote:
> RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
> with R-Car Gen3, therefore add the relevant documentation.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>   Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
> index 9f365c1..a5bf04d 100644
> --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
> @@ -10,6 +10,7 @@ Required properties:
>   		 - "renesas,r8a7745-wdt" (RZ/G1E)
>   		 - "renesas,r8a77470-wdt" (RZ/G1C)
>   		 - "renesas,r8a774a1-wdt" (RZ/G2M)
> +		 - "renesas,r8a774b1-wdt" (RZ/G2N)
>   		 - "renesas,r8a774c0-wdt" (RZ/G2E)
>   	         - "renesas,r8a7790-wdt" (R-Car H2)
>   	         - "renesas,r8a7791-wdt" (R-Car M2-W)
> 

Re: [PATCH 1/7] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:35 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
> with R-Car Gen3, therefore add the relevant documentation.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/7] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

[Rob Herring]

On Fri,  4 Oct 2019 09:35:27 +0100, Fabrizio Castro wrote:
> RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
> with R-Car Gen3, therefore add the relevant documentation.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied, thanks.

Rob

[PATCH 2/7] dt-bindings: spi: sh-msiof: Add r8a774b1 support

[Fabrizio Castro]

Document RZ/G2N (R8A774B1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

---

This patch depends on https://patchwork.kernel.org/patch/11162283/
---
 Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
index 4afaa48..b6c1dd2 100644
--- a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
@@ -35,6 +35,7 @@ properties:
       - items:
           - enum:
               - renesas,msiof-r8a774a1      # RZ/G2M
+              - renesas,msiof-r8a774b1      # RZ/G2N
               - renesas,msiof-r8a774c0      # RZ/G2E
               - renesas,msiof-r8a7795       # R-Car H3
               - renesas,msiof-r8a7796       # R-Car M3-W
-- 
2.7.4

Re: [PATCH 2/7] dt-bindings: spi: sh-msiof: Add r8a774b1 support

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:35 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Document RZ/G2N (R8A774B1) SoC bindings.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Applied "dt-bindings: spi: sh-msiof: Add r8a774b1 support" to the spi tree

[Mark Brown]

The patch

   dt-bindings: spi: sh-msiof: Add r8a774b1 support

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.5

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 97f41c68b83ea5216dbf3ac51fd86b0fbd399a97 Mon Sep 17 00:00:00 2001
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Date: Fri, 4 Oct 2019 09:35:28 +0100
Subject: [PATCH] dt-bindings: spi: sh-msiof: Add r8a774b1 support

Document RZ/G2N (R8A774B1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1570178133-21532-3-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
index 4afaa48c1666..b6c1dd2a9c5e 100644
--- a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
@@ -35,6 +35,7 @@ properties:
       - items:
           - enum:
               - renesas,msiof-r8a774a1      # RZ/G2M
+              - renesas,msiof-r8a774b1      # RZ/G2N
               - renesas,msiof-r8a774c0      # RZ/G2E
               - renesas,msiof-r8a7795       # R-Car H3
               - renesas,msiof-r8a7796       # R-Car M3-W
-- 
2.20.1

[PATCH 3/7] dt-bindings: PCI: rcar: Add device tree support for r8a774b1

[Fabrizio Castro]

Add PCIe support for the RZ/G2N (a.k.a. R8A774B1).

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index 45bba9f..12702c8 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -4,6 +4,7 @@ Required properties:
 compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
 	    "renesas,pcie-r8a7744" for the R8A7744 SoC;
 	    "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
+	    "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
 	    "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
 	    "renesas,pcie-r8a7779" for the R8A7779 SoC;
 	    "renesas,pcie-r8a7790" for the R8A7790 SoC;
-- 
2.7.4

Re: [PATCH 3/7] dt-bindings: PCI: rcar: Add device tree support for r8a774b1

[Andrew Murray]

On Fri, Oct 04, 2019 at 09:35:29AM +0100, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2N (a.k.a. R8A774B1).
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
> index 45bba9f..12702c8 100644
> --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
> @@ -4,6 +4,7 @@ Required properties:
>  compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
>  	    "renesas,pcie-r8a7744" for the R8A7744 SoC;
>  	    "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
> +	    "renesas,pcie-r8a774b1" for the R8A774B1 SoC;

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  	    "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
>  	    "renesas,pcie-r8a7779" for the R8A7779 SoC;
>  	    "renesas,pcie-r8a7790" for the R8A7790 SoC;
> -- 
> 2.7.4
> 

Re: [PATCH 3/7] dt-bindings: PCI: rcar: Add device tree support for r8a774b1

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:35 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add PCIe support for the RZ/G2N (a.k.a. R8A774B1).
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/7] dt-bindings: PCI: rcar: Add device tree support for r8a774b1

[Rob Herring]

On Fri,  4 Oct 2019 09:35:29 +0100, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2N (a.k.a. R8A774B1).
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied, thanks.

Rob

[PATCH 4/7] arm64: dts: renesas: r8a774b1: Add RWDT node

[Fabrizio Castro]

Populate the device tree node for the Watchdog Timer (RWDT)
controller on the Renesas RZ/G2N (r8a774b1) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 538e9ce..3f885a6 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -151,8 +151,13 @@
 		ranges;
 
 		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a774b1-wdt",
+				     "renesas,rcar-gen3-wdt";
 			reg = <0 0xe6020000 0 0x0c>;
-			/* placeholder */
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
+			status = "disabled";
 		};
 
 		gpio0: gpio@e6050000 {
-- 
2.7.4

Re: [PATCH 4/7] arm64: dts: renesas: r8a774b1: Add RWDT node

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Populate the device tree node for the Watchdog Timer (RWDT)
> controller on the Renesas RZ/G2N (r8a774b1) SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 5/7] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Fabrizio Castro]

Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
SoC (a.k.a. r8a774b1).

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 62 +++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 3f885a6..3bd0b47 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1115,6 +1115,68 @@
 			status = "disabled";
 		};
 
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		rcar_sound: sound@ec500000 {
 			reg = <0 0xec500000 0 0x1000>, /* SCU */
 			      <0 0xec5a0000 0 0x100>,  /* ADG */
-- 
2.7.4

Re: [PATCH 5/7] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
> SoC (a.k.a. r8a774b1).
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

[Fabrizio Castro]

This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 3bd0b47..0163b284 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1304,19 +1304,57 @@
 		};
 
 		pciec0: pcie@fe000000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xfe000000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 319>;
+			status = "disabled";
 		};
 
 		pciec1: pcie@ee800000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xee800000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+				  0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+				  0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+				  0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 318>;
+			status = "disabled";
 		};
 
 		fdp1@fe940000 {
-- 
2.7.4

Re: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

[Andrew Murray]

On Fri, Oct 04, 2019 at 09:35:32AM +0100, Fabrizio Castro wrote:
> This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
>  1 file changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> index 3bd0b47..0163b284 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> @@ -1304,19 +1304,57 @@
>  		};
>  
>  		pciec0: pcie@fe000000 {
> +			compatible = "renesas,pcie-r8a774b1",
> +				     "renesas,pcie-rcar-gen3";
>  			reg = <0 0xfe000000 0 0x80000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			bus-range = <0x00 0xff>;
> -			/* placeholder */
> +			device_type = "pci";
> +			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
> +				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
> +				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
> +				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
> +			/* Map all possible DDR as inbound ranges */
> +			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> +			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0>;
> +			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
> +			clock-names = "pcie", "pcie_bus";
> +			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
> +			resets = <&cpg 319>;
> +			status = "disabled";
>  		};
>  
>  		pciec1: pcie@ee800000 {
> +			compatible = "renesas,pcie-r8a774b1",
> +				     "renesas,pcie-rcar-gen3";
>  			reg = <0 0xee800000 0 0x80000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			bus-range = <0x00 0xff>;
> -			/* placeholder */
> +			device_type = "pci";
> +			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
> +				  0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
> +				  0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
> +				  0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
> +			/* Map all possible DDR as inbound ranges */
> +			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> +			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0>;
> +			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
> +			clock-names = "pcie", "pcie_bus";
> +			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
> +			resets = <&cpg 318>;
> +			status = "disabled";
>  		};
>  
>  		fdp1@fe940000 {
> -- 
> 2.7.4
> 

Re: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 7/7] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1

[Fabrizio Castro]

The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
and use pciec1 physical interface for SATA (as SATA and PCIE1 share
the same physical interface), therefore move pciec1 enabling away
from hihope-rzg2-ex.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi          | 4 ----
 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 4 ++++
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index ae1ef2d..63e407a 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -85,10 +85,6 @@
 	status = "okay";
 };
 
-&pciec1 {
-	status = "okay";
-};
-
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
index 6e33a3b..c754fca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
@@ -13,3 +13,7 @@
 	compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
 		     "renesas,r8a774a1";
 };
+
+&pciec1 {
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH 7/7] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1

[Geert Uytterhoeven]

On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
> and use pciec1 physical interface for SATA (as SATA and PCIE1 share
> the same physical interface), therefore move pciec1 enabling away
> from hihope-rzg2-ex.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds