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Tue, 13 Jul 2021 18:58:53 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id r6sm443341ilh.35.2021.07.13.18.58.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 18:58:53 -0700 (PDT) Received: (nullmailer pid 1286017 invoked by uid 1000); Wed, 14 Jul 2021 01:58:49 -0000 Date: Tue, 13 Jul 2021 19:58:49 -0600 From: Rob Herring To: Christine Zhu Cc: wim@linux-watchdog.org, linux@roeck-us.net, matthias.bgg@gmail.com, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, seiya.wang@mediatek.com Subject: Re: [v5,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file Message-ID: <20210714015849.GA1283155@robh.at.kernel.org> References: <20210628113730.26107-1-Christine.Zhu@mediatek.com> <20210628113730.26107-3-Christine.Zhu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210628113730.26107-3-Christine.Zhu@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org On Mon, Jun 28, 2021 at 07:37:30PM +0800, Christine Zhu wrote: > From: "Christine Zhu" > > Add toprgu reset-controller head file for MT8195 platform. s/head/header/ And the subject too. > > Signed-off-by: Christine Zhu > --- > .../reset-controller/mt8195-resets.h | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h > new file mode 100644 > index 000000000000..7ec27a64afc7 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt8195-resets.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. > +/* > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Crystal Guo According to the S-o-b and patch author, you are the author. > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 > + > +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 > +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 > +#define MT8195_TOPRGU_APU_SW_RST 2 > +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 > +#define MT8195_TOPRGU_MMSYS_SW_RST 7 > +#define MT8195_TOPRGU_MFG_SW_RST 8 > +#define MT8195_TOPRGU_VENC_SW_RST 9 > +#define MT8195_TOPRGU_VDEC_SW_RST 10 > +#define MT8195_TOPRGU_IMG_SW_RST 11 > +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 > +#define MT8195_TOPRGU_AUDIO_SW_RST 14 > +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 > +#define MT8195_TOPRGU_EDPTX_SW_RST 16 > +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 > +#define MT8195_TOPRGU_DPTX_SW_RST 22 > +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 > + > +#define MT8195_TOPRGU_SW_RST_NUM 16 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ > -- > 2.18.0 > >