* [PATCH v8 0/2] ASoC: mt8183: fix audio playback slowly after playback @ 2020-01-03 9:37 Jiaxin Yu 2020-01-03 9:37 ` [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2020-01-03 9:37 ` [PATCH 2/2] [PATCH v8 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 0 siblings, 2 replies; 5+ messages in thread From: Jiaxin Yu @ 2020-01-03 9:37 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu This series patches add reset controller for MT8183, and audio will use it in machine driver during bootup, they depend on the for-next. V8 changes: 1. Delete cast: (struct mtk_wdt_data *) V7 changes: 1. Delete no use code. v6 changes: 1. Simplify toprug_reset_assert() & toprug_reset_deassert(). 2. Add members for mt2712_data & mt8183_data. v5 changes: 1. Add Signed-off-by tag and Reviewed-by tag. v4 changes: 1. Fixed wrong signed-off as correct mail suffix. 2. Fixed patch subject that add patch version. v3 changes: 1. https://patchwork.kernel.org/patch/11164283/ and https://patchwork.kernel.org/patch/11164305/ has been merged. 2. Change the name of mtk_wdt_compatible to mtk_wdt_data. 3. Remove toprgu_reset struct and use mtk_wdt_dev instead. 4. Get the value of sw_rst_num from .h file. 5. Adddd mt2712-resets.h for mt2712. 6. Improve commit message. v2 changes: 1. remove "WIP" that in the title of patches 2. add hyper link for the patch that depends on 3. patchwork list: https://patchwork.kernel.org/cover/11164285/ https://patchwork.kernel.org/patch/11164295/ https://patchwork.kernel.org/patch/11164299/ https://patchwork.kernel.org/patch/11164283/ https://patchwork.kernel.org/patch/11164305/ v1 changes: 1. patchwork list: https://patchwork.kernel.org/cover/11164173/ https://patchwork.kernel.org/patch/11164181/ https://patchwork.kernel.org/patch/11164185/ https://patchwork.kernel.org/patch/11164187/ https://patchwork.kernel.org/patch/11164175/ Jiaxin Yu (2): dt-bindings: mediatek: mt8183: Add #reset-cells watchdog: mtk_wdt: mt8183: Add reset controller drivers/watchdog/mtk_wdt.c | 105 +++++++++++++++++- .../reset-controller/mt2712-resets.h | 22 ++++ .../reset-controller/mt8183-resets.h | 17 +++ 3 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h -- 2.18.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-03 9:37 [PATCH v8 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu @ 2020-01-03 9:37 ` Jiaxin Yu 2020-01-03 22:12 ` Rob Herring 2020-01-04 16:56 ` Guenter Roeck 2020-01-03 9:37 ` [PATCH 2/2] [PATCH v8 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 1 sibling, 2 replies; 5+ messages in thread From: Jiaxin Yu @ 2020-01-03 9:37 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu Add #reset-cells property and update example Change-Id: If3f4f0170d417819facff1fd0a0e5e3c6cc9944d Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> --- .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h new file mode 100644 index 000000000000..9e7ee762f076 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt2712-resets.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 + +#define MT2712_TOPRGU_INFRA_SW_RST 0 +#define MT2712_TOPRGU_MM_SW_RST 1 +#define MT2712_TOPRGU_MFG_SW_RST 2 +#define MT2712_TOPRGU_VENC_SW_RST 3 +#define MT2712_TOPRGU_VDEC_SW_RST 4 +#define MT2712_TOPRGU_IMG_SW_RST 5 +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +#define MT2712_TOPRGU_USB_SW_RST 9 +#define MT2712_TOPRGU_APMIXED_SW_RST 10 + +#define MT2712_TOPRGU_SW_RST_NUM 11 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..a1bbd41e0d12 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,21 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_INFRACFG_SW_RST_NUM 128 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 19 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-03 9:37 ` [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2020-01-03 22:12 ` Rob Herring 2020-01-04 16:56 ` Guenter Roeck 1 sibling, 0 replies; 5+ messages in thread From: Rob Herring @ 2020-01-03 22:12 UTC (permalink / raw) To: Jiaxin Yu Cc: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin, yingjoe.chen, sboyd On Fri, Jan 03, 2020 at 05:37:24PM +0800, Jiaxin Yu wrote: > Add #reset-cells property and update example > > Change-Id: If3f4f0170d417819facff1fd0a0e5e3c6cc9944d Drop this. > Signed-off-by: yong.liang <yong.liang@mediatek.com> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > --- > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h What happened to the binding doc change? > > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > new file mode 100644 > index 000000000000..9e7ee762f076 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Yong Liang <yong.liang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > + > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > +#define MT2712_TOPRGU_MM_SW_RST 1 > +#define MT2712_TOPRGU_MFG_SW_RST 2 > +#define MT2712_TOPRGU_VENC_SW_RST 3 > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > +#define MT2712_TOPRGU_IMG_SW_RST 5 > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT2712_TOPRGU_USB_SW_RST 9 > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > + > +#define MT2712_TOPRGU_SW_RST_NUM 11 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > index 8804e34ebdd4..a1bbd41e0d12 100644 > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > @@ -78,4 +78,21 @@ > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > +#define MT8183_INFRACFG_SW_RST_NUM 128 > + > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > + > +#define MT8183_TOPRGU_SW_RST_NUM 19 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ > -- > 2.18.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-03 9:37 ` [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2020-01-03 22:12 ` Rob Herring @ 2020-01-04 16:56 ` Guenter Roeck 1 sibling, 0 replies; 5+ messages in thread From: Guenter Roeck @ 2020-01-04 16:56 UTC (permalink / raw) To: Jiaxin Yu, yong.liang, wim, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd On 1/3/20 1:37 AM, Jiaxin Yu wrote: > Add #reset-cells property and update example > > Change-Id: If3f4f0170d417819facff1fd0a0e5e3c6cc9944d No Change-Id in upstream kernel code, please. Guenter > Signed-off-by: yong.liang <yong.liang@mediatek.com> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > --- > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > new file mode 100644 > index 000000000000..9e7ee762f076 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Yong Liang <yong.liang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > + > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > +#define MT2712_TOPRGU_MM_SW_RST 1 > +#define MT2712_TOPRGU_MFG_SW_RST 2 > +#define MT2712_TOPRGU_VENC_SW_RST 3 > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > +#define MT2712_TOPRGU_IMG_SW_RST 5 > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT2712_TOPRGU_USB_SW_RST 9 > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > + > +#define MT2712_TOPRGU_SW_RST_NUM 11 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > index 8804e34ebdd4..a1bbd41e0d12 100644 > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > @@ -78,4 +78,21 @@ > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > +#define MT8183_INFRACFG_SW_RST_NUM 128 > + > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > + > +#define MT8183_TOPRGU_SW_RST_NUM 19 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] [PATCH v8 2/2] watchdog: mtk_wdt: mt8183: Add reset controller 2020-01-03 9:37 [PATCH v8 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2020-01-03 9:37 ` [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2020-01-03 9:37 ` Jiaxin Yu 1 sibling, 0 replies; 5+ messages in thread From: Jiaxin Yu @ 2020-01-03 9:37 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu Add reset controller API in watchdog driver. Besides watchdog, MTK toprgu module alsa provide sub-system (eg, audio, camera, codec and connectivity) software reset functionality. Change-Id: I1504e3a683b3d96722f0cabe0576d0d2fd3453f1 Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> --- drivers/watchdog/mtk_wdt.c | 105 ++++++++++++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 9c3d0033260d..d6a6393f609d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,6 +9,9 @@ * Based on sunxi_wdt.c */ +#include <dt-bindings/reset-controller/mt2712-resets.h> +#include <dt-bindings/reset-controller/mt8183-resets.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -16,10 +19,11 @@ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset-controller.h> #include <linux/types.h> #include <linux/watchdog.h> -#include <linux/delay.h> #define WDT_MAX_TIMEOUT 31 #define WDT_MIN_TIMEOUT 1 @@ -44,6 +48,9 @@ #define WDT_SWRST 0x14 #define WDT_SWRST_KEY 0x1209 +#define WDT_SWSYSRST 0x18U +#define WDT_SWSYS_RST_KEY 0x88000000 + #define DRV_NAME "mtk-wdt" #define DRV_VERSION "1.0" @@ -53,8 +60,94 @@ static unsigned int timeout; struct mtk_wdt_dev { struct watchdog_device wdt_dev; void __iomem *wdt_base; + spinlock_t lock; /* protects WDT_SWSYSRST reg */ + struct reset_controller_dev rcdev; +}; + +struct mtk_wdt_data { + int toprgu_sw_rst_num; }; +static const struct mtk_wdt_data mt2712_data = { + .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, +}; + +static const struct mtk_wdt_data mt8183_data = { + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, +}; + +static int toprgu_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + unsigned int tmp; + unsigned long flags; + struct mtk_wdt_dev *data = + container_of(rcdev, struct mtk_wdt_dev, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = readl(data->wdt_base + WDT_SWSYSRST); + if (assert) + tmp |= BIT(id); + else + tmp &= ~BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->wdt_base + WDT_SWSYSRST); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return toprgu_reset_update(rcdev, id, true); +} + +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return toprgu_reset_update(rcdev, id, false); +} + +static int toprgu_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = toprgu_reset_assert(rcdev, id); + if (ret) + return ret; + + return toprgu_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops toprgu_reset_ops = { + .assert = toprgu_reset_assert, + .deassert = toprgu_reset_deassert, + .reset = toprgu_reset, +}; + +static int toprgu_register_reset_controller(struct platform_device *pdev, + int rst_num) +{ + int ret; + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); + + spin_lock_init(&mtk_wdt->lock); + + mtk_wdt->rcdev.owner = THIS_MODULE; + mtk_wdt->rcdev.nr_resets = rst_num; + mtk_wdt->rcdev.ops = &toprgu_reset_ops; + mtk_wdt->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); + if (ret != 0) + dev_err(&pdev->dev, + "couldn't register wdt reset controller: %d\n", ret); + return ret; +} + static int mtk_wdt_restart(struct watchdog_device *wdt_dev, unsigned long action, void *data) { @@ -155,6 +248,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_wdt_dev *mtk_wdt; + const struct mtk_wdt_data *wdt_data; int err; mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); @@ -190,6 +284,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", mtk_wdt->wdt_dev.timeout, nowayout); + wdt_data = of_device_get_match_data(dev); + if (wdt_data) { + err = toprgu_register_reset_controller(pdev, + wdt_data->toprgu_sw_rst_num); + if (err) + return err; + } return 0; } @@ -218,7 +319,9 @@ static int mtk_wdt_resume(struct device *dev) #endif static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); -- 2.18.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-04 16:56 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-03 9:37 [PATCH v8 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2020-01-03 9:37 ` [PATCH 1/2] [PATCH v8 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2020-01-03 22:12 ` Rob Herring 2020-01-04 16:56 ` Guenter Roeck 2020-01-03 9:37 ` [PATCH 2/2] [PATCH v8 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu
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