* [PATCH v11 0/3] ASoC: mt8183: fix audio playback slowly after playback @ 2020-01-10 7:04 Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu ` (2 more replies) 0 siblings, 3 replies; 9+ messages in thread From: Jiaxin Yu @ 2020-01-10 7:04 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu This series patches add reset controller for MT8183 and MT2712, and audio will use it in machine driver during bootup, they depend on the for-next. v11 changes: 1. Create a new patch for MT2712. v10 changes: 1. Modify mtk-wdt.txt dt-bindings. v9 changes: 1. Remove Change-Id. v8 changes: 1. Delete cast: (struct mtk_wdt_data *) v7 changes: 1. Delete no use code. v6 changes: 1. Simplify toprug_reset_assert() & toprug_reset_deassert(). 2. Add members for mt2712_data & mt8183_data. v5 changes: 1. Add Signed-off-by tag and Reviewed-by tag. v4 changes: 1. Fixed wrong signed-off as correct mail suffix. 2. Fixed patch subject that add patch version. v3 changes: 1. https://patchwork.kernel.org/patch/11164283/ and https://patchwork.kernel.org/patch/11164305/ has been merged. 2. Change the name of mtk_wdt_compatible to mtk_wdt_data. 3. Remove toprgu_reset struct and use mtk_wdt_dev instead. 4. Get the value of sw_rst_num from .h file. 5. Adddd mt2712-resets.h for mt2712. 6. Improve commit message. v2 changes: 1. remove "WIP" that in the title of patches 2. add hyper link for the patch that depends on 3. patchwork list: https://patchwork.kernel.org/cover/11164285/ https://patchwork.kernel.org/patch/11164295/ https://patchwork.kernel.org/patch/11164299/ https://patchwork.kernel.org/patch/11164283/ https://patchwork.kernel.org/patch/11164305/ v1 changes: 1. patchwork list: https://patchwork.kernel.org/cover/11164173/ https://patchwork.kernel.org/patch/11164181/ https://patchwork.kernel.org/patch/11164185/ https://patchwork.kernel.org/patch/11164187/ https://patchwork.kernel.org/patch/11164175/ Jiaxin Yu (3): dt-bindings: mediatek: mt8183: Add #reset-cells watchdog: mtk_wdt: mt8183: Add reset controller watchdog: mtk_wdt: mt2712: Add reset controller .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 +- drivers/watchdog/mtk_wdt.c | 105 +++++++++++++++++- .../reset-controller/mt2712-resets.h | 22 ++++ .../reset-controller/mt8183-resets.h | 17 +++ 4 files changed, 150 insertions(+), 4 deletions(-) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h -- 2.18.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-10 7:04 [PATCH v11 0/3] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu @ 2020-01-10 7:04 ` Jiaxin Yu 2020-01-13 6:10 ` Nicolas Boichat 2020-01-10 7:04 ` [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: " Jiaxin Yu 2 siblings, 1 reply; 9+ messages in thread From: Jiaxin Yu @ 2020-01-10 7:04 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu Add #reset-cells property and update example Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <groeck7@gmail.com> --- .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ 3 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 92181b648f52..5a76ac262f8d 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,6 +4,7 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 @@ -14,11 +15,14 @@ Required properties: Optional properties: - timeout-sec: contains the watchdog timeout in seconds. +- #reset-cells: Should be 1. Example: -wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x18>; +watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; timeout-sec = <10>; + #reset-cells = <1>; }; diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h new file mode 100644 index 000000000000..9e7ee762f076 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt2712-resets.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 + +#define MT2712_TOPRGU_INFRA_SW_RST 0 +#define MT2712_TOPRGU_MM_SW_RST 1 +#define MT2712_TOPRGU_MFG_SW_RST 2 +#define MT2712_TOPRGU_VENC_SW_RST 3 +#define MT2712_TOPRGU_VDEC_SW_RST 4 +#define MT2712_TOPRGU_IMG_SW_RST 5 +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +#define MT2712_TOPRGU_USB_SW_RST 9 +#define MT2712_TOPRGU_APMIXED_SW_RST 10 + +#define MT2712_TOPRGU_SW_RST_NUM 11 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..a1bbd41e0d12 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,21 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_INFRACFG_SW_RST_NUM 128 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 19 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-10 7:04 ` [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2020-01-13 6:10 ` Nicolas Boichat 2020-01-13 9:12 ` Yong Liang 0 siblings, 1 reply; 9+ messages in thread From: Nicolas Boichat @ 2020-01-13 6:10 UTC (permalink / raw) To: Jiaxin Yu Cc: Yong Liang, wim, linux, Philipp Zabel, Matthias Brugger, linux-watchdog, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support, Devicetree List, chang-an.chen, freddy.hsin, Yingjoe Chen, Stephen Boyd Jiaxin, On Fri, Jan 10, 2020 at 3:04 PM Jiaxin Yu <jiaxin.yu@mediatek.com> wrote: > > Add #reset-cells property and update example > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: Guenter Roeck <groeck7@gmail.com> From previous feedback (https://patchwork.kernel.org/patch/11318687/#23086211), it seems like we lost track of which exact version had the Reviewed-By, so I'd just drop all those tags and let people review again. > --- It would have been nice to mention that this patch depends on https://patchwork.kernel.org/patch/11311241/ (as your example makes use of it below). > .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ > 3 files changed, 46 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > index 92181b648f52..5a76ac262f8d 100644 > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > @@ -4,6 +4,7 @@ Required properties: > > - compatible should contain: > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 > + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 Please separate this as another patch. > "mediatek,mt6589-wdt": for MT6589 > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 > @@ -14,11 +15,14 @@ Required properties: > > Optional properties: > - timeout-sec: contains the watchdog timeout in seconds. > +- #reset-cells: Should be 1. > > Example: > > -wdt: watchdog@10000000 { > - compatible = "mediatek,mt6589-wdt"; > - reg = <0x10000000 0x18>; > +watchdog: watchdog@10007000 { > + compatible = "mediatek,mt8183-wdt", > + "mediatek,mt6589-wdt"; > + reg = <0 0x10007000 0 0x100>; > timeout-sec = <10>; > + #reset-cells = <1>; > }; > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > new file mode 100644 > index 000000000000..9e7ee762f076 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Yong Liang <yong.liang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > + > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > +#define MT2712_TOPRGU_MM_SW_RST 1 > +#define MT2712_TOPRGU_MFG_SW_RST 2 > +#define MT2712_TOPRGU_VENC_SW_RST 3 > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > +#define MT2712_TOPRGU_IMG_SW_RST 5 > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT2712_TOPRGU_USB_SW_RST 9 > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > + > +#define MT2712_TOPRGU_SW_RST_NUM 11 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > index 8804e34ebdd4..a1bbd41e0d12 100644 > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > @@ -78,4 +78,21 @@ > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > +#define MT8183_INFRACFG_SW_RST_NUM 128 > + > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > + > +#define MT8183_TOPRGU_SW_RST_NUM 19 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ > -- > 2.18.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-13 6:10 ` Nicolas Boichat @ 2020-01-13 9:12 ` Yong Liang 2020-01-13 9:20 ` Philipp Zabel 0 siblings, 1 reply; 9+ messages in thread From: Yong Liang @ 2020-01-13 9:12 UTC (permalink / raw) To: Nicolas Boichat Cc: Jiaxin Yu (俞家鑫), wim, linux, Philipp Zabel, Matthias Brugger, linux-watchdog, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support, Devicetree List, Chang-An Chen (陳昶安), Freddy Hsin (辛恒豐), Yingjoe Chen (陳英洲), Stephen Boyd On Mon, 2020-01-13 at 14:10 +0800, Nicolas Boichat wrote: > Jiaxin, > > On Fri, Jan 10, 2020 at 3:04 PM Jiaxin Yu <jiaxin.yu@mediatek.com> wrote: > > > > Add #reset-cells property and update example > > > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Reviewed-by: Guenter Roeck <groeck7@gmail.com> > > From previous feedback > (https://patchwork.kernel.org/patch/11318687/#23086211), it seems like > we lost track of which exact version had the Reviewed-By, so I'd just > drop all those tags and let people review again. > Need I do someting? > > --- > > It would have been nice to mention that this patch depends on > https://patchwork.kernel.org/patch/11311241/ (as your example makes > use of it below). Can I drop the mtk-wdt.txt of https://patchwork.kernel.org/patch/11311241/? And I want add 8183 in mtk-wdt.txt in this patch. > > .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- > > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > > .../reset-controller/mt8183-resets.h | 17 ++++++++++++++ > > 3 files changed, 46 insertions(+), 3 deletions(-) > > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h > > > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > > index 92181b648f52..5a76ac262f8d 100644 > > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > > @@ -4,6 +4,7 @@ Required properties: > > > > - compatible should contain: > > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 > > + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 > > Please separate this as another patch. So I can send mtk-wdt.c(MT2712) and mt2712-resets.h in one patch and send mtk-wdt.c(MT8183) and mt8183-resets.h in another patch? > > > "mediatek,mt6589-wdt": for MT6589 > > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 > > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 > > @@ -14,11 +15,14 @@ Required properties: > > > > Optional properties: > > - timeout-sec: contains the watchdog timeout in seconds. > > +- #reset-cells: Should be 1. > > > > Example: > > > > -wdt: watchdog@10000000 { > > - compatible = "mediatek,mt6589-wdt"; > > - reg = <0x10000000 0x18>; > > +watchdog: watchdog@10007000 { > > + compatible = "mediatek,mt8183-wdt", > > + "mediatek,mt6589-wdt"; > > + reg = <0 0x10007000 0 0x100>; > > timeout-sec = <10>; > > + #reset-cells = <1>; > > }; > > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > > new file mode 100644 > > index 000000000000..9e7ee762f076 > > --- /dev/null > > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > > @@ -0,0 +1,22 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2019 MediaTek Inc. > > + * Author: Yong Liang <yong.liang@mediatek.com> > > + */ > > + > > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > > + > > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > > +#define MT2712_TOPRGU_MM_SW_RST 1 > > +#define MT2712_TOPRGU_MFG_SW_RST 2 > > +#define MT2712_TOPRGU_VENC_SW_RST 3 > > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > > +#define MT2712_TOPRGU_IMG_SW_RST 5 > > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > > +#define MT2712_TOPRGU_USB_SW_RST 9 > > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > > + > > +#define MT2712_TOPRGU_SW_RST_NUM 11 > > + > > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > > index 8804e34ebdd4..a1bbd41e0d12 100644 > > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > > @@ -78,4 +78,21 @@ > > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > > > +#define MT8183_INFRACFG_SW_RST_NUM 128 > > + > > +#define MT8183_TOPRGU_MM_SW_RST 1 > > +#define MT8183_TOPRGU_MFG_SW_RST 2 > > +#define MT8183_TOPRGU_VENC_SW_RST 3 > > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > > +#define MT8183_TOPRGU_IMG_SW_RST 5 > > +#define MT8183_TOPRGU_MD_SW_RST 7 > > +#define MT8183_TOPRGU_CONN_SW_RST 9 > > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > > + > > +#define MT8183_TOPRGU_SW_RST_NUM 19 > > + > > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ > > -- > > 2.18.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells 2020-01-13 9:12 ` Yong Liang @ 2020-01-13 9:20 ` Philipp Zabel 0 siblings, 0 replies; 9+ messages in thread From: Philipp Zabel @ 2020-01-13 9:20 UTC (permalink / raw) To: Yong Liang, Nicolas Boichat Cc: Jiaxin Yu (俞家鑫), wim, linux, Matthias Brugger, linux-watchdog, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support, Devicetree List, Chang-An Chen (陳昶安), Freddy Hsin (辛恒豐), Yingjoe Chen (陳英洲), Stephen Boyd On Mon, 2020-01-13 at 17:12 +0800, Yong Liang wrote: > On Mon, 2020-01-13 at 14:10 +0800, Nicolas Boichat wrote: > > Jiaxin, > > > > On Fri, Jan 10, 2020 at 3:04 PM Jiaxin Yu <jiaxin.yu@mediatek.com> wrote: > > > Add #reset-cells property and update example > > > > > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > > > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > > > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> You can keep my R-b on all three patches, this one specifically referred to the dt-bindings/reset-controller header files. regards Philipp ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller 2020-01-10 7:04 [PATCH v11 0/3] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2020-01-10 7:04 ` Jiaxin Yu 2020-01-13 6:19 ` Nicolas Boichat 2020-01-10 7:04 ` [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: " Jiaxin Yu 2 siblings, 1 reply; 9+ messages in thread From: Jiaxin Yu @ 2020-01-10 7:04 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu Add reset controller API in watchdog driver. Besides watchdog, MTK toprgu module alsa provide sub-system (eg, audio, camera, codec and connectivity) software reset functionality. Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <groeck7@gmail.com> --- drivers/watchdog/mtk_wdt.c | 99 +++++++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 9c3d0033260d..e88aacb0404d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,6 +9,8 @@ * Based on sunxi_wdt.c */ +#include <dt-bindings/reset-controller/mt8183-resets.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -16,10 +18,11 @@ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset-controller.h> #include <linux/types.h> #include <linux/watchdog.h> -#include <linux/delay.h> #define WDT_MAX_TIMEOUT 31 #define WDT_MIN_TIMEOUT 1 @@ -44,6 +47,9 @@ #define WDT_SWRST 0x14 #define WDT_SWRST_KEY 0x1209 +#define WDT_SWSYSRST 0x18U +#define WDT_SWSYS_RST_KEY 0x88000000 + #define DRV_NAME "mtk-wdt" #define DRV_VERSION "1.0" @@ -53,8 +59,90 @@ static unsigned int timeout; struct mtk_wdt_dev { struct watchdog_device wdt_dev; void __iomem *wdt_base; + spinlock_t lock; /* protects WDT_SWSYSRST reg */ + struct reset_controller_dev rcdev; +}; + +struct mtk_wdt_data { + int toprgu_sw_rst_num; }; +static const struct mtk_wdt_data mt8183_data = { + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, +}; + +static int toprgu_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + unsigned int tmp; + unsigned long flags; + struct mtk_wdt_dev *data = + container_of(rcdev, struct mtk_wdt_dev, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = readl(data->wdt_base + WDT_SWSYSRST); + if (assert) + tmp |= BIT(id); + else + tmp &= ~BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->wdt_base + WDT_SWSYSRST); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return toprgu_reset_update(rcdev, id, true); +} + +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return toprgu_reset_update(rcdev, id, false); +} + +static int toprgu_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = toprgu_reset_assert(rcdev, id); + if (ret) + return ret; + + return toprgu_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops toprgu_reset_ops = { + .assert = toprgu_reset_assert, + .deassert = toprgu_reset_deassert, + .reset = toprgu_reset, +}; + +static int toprgu_register_reset_controller(struct platform_device *pdev, + int rst_num) +{ + int ret; + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); + + spin_lock_init(&mtk_wdt->lock); + + mtk_wdt->rcdev.owner = THIS_MODULE; + mtk_wdt->rcdev.nr_resets = rst_num; + mtk_wdt->rcdev.ops = &toprgu_reset_ops; + mtk_wdt->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); + if (ret != 0) + dev_err(&pdev->dev, + "couldn't register wdt reset controller: %d\n", ret); + return ret; +} + static int mtk_wdt_restart(struct watchdog_device *wdt_dev, unsigned long action, void *data) { @@ -155,6 +243,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_wdt_dev *mtk_wdt; + const struct mtk_wdt_data *wdt_data; int err; mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); @@ -190,6 +279,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", mtk_wdt->wdt_dev.timeout, nowayout); + wdt_data = of_device_get_match_data(dev); + if (wdt_data) { + err = toprgu_register_reset_controller(pdev, + wdt_data->toprgu_sw_rst_num); + if (err) + return err; + } return 0; } @@ -219,6 +315,7 @@ static int mtk_wdt_resume(struct device *dev) static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt6589-wdt" }, + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); -- 2.18.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller 2020-01-10 7:04 ` [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu @ 2020-01-13 6:19 ` Nicolas Boichat 0 siblings, 0 replies; 9+ messages in thread From: Nicolas Boichat @ 2020-01-13 6:19 UTC (permalink / raw) To: Jiaxin Yu Cc: Yong Liang, wim, linux, Philipp Zabel, Matthias Brugger, linux-watchdog, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support, Devicetree List, chang-an.chen, freddy.hsin, Yingjoe Chen, Stephen Boyd On Fri, Jan 10, 2020 at 3:04 PM Jiaxin Yu <jiaxin.yu@mediatek.com> wrote: > > Add reset controller API in watchdog driver. > Besides watchdog, MTK toprgu module alsa provide sub-system (eg, audio, > camera, codec and connectivity) software reset functionality. > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Since there was a doubt about the history of the tags, trying to detangle: > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> This comes from v7 (https://patchwork.kernel.org/patch/11311039/), that also had MT2712, but otherwise the patch is functionally similar. > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: Guenter Roeck <groeck7@gmail.com> I don't see these tags anywhere in the history, please drop them. > --- > drivers/watchdog/mtk_wdt.c | 99 +++++++++++++++++++++++++++++++++++++- > 1 file changed, 98 insertions(+), 1 deletion(-) > > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index 9c3d0033260d..e88aacb0404d 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -9,6 +9,8 @@ > * Based on sunxi_wdt.c > */ > > +#include <dt-bindings/reset-controller/mt8183-resets.h> > +#include <linux/delay.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/io.h> > @@ -16,10 +18,11 @@ > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/of.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/reset-controller.h> > #include <linux/types.h> > #include <linux/watchdog.h> > -#include <linux/delay.h> > > #define WDT_MAX_TIMEOUT 31 > #define WDT_MIN_TIMEOUT 1 > @@ -44,6 +47,9 @@ > #define WDT_SWRST 0x14 > #define WDT_SWRST_KEY 0x1209 > > +#define WDT_SWSYSRST 0x18U > +#define WDT_SWSYS_RST_KEY 0x88000000 > + > #define DRV_NAME "mtk-wdt" > #define DRV_VERSION "1.0" > > @@ -53,8 +59,90 @@ static unsigned int timeout; > struct mtk_wdt_dev { > struct watchdog_device wdt_dev; > void __iomem *wdt_base; > + spinlock_t lock; /* protects WDT_SWSYSRST reg */ > + struct reset_controller_dev rcdev; > +}; > + > +struct mtk_wdt_data { > + int toprgu_sw_rst_num; > }; > > +static const struct mtk_wdt_data mt8183_data = { > + .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > +}; > + > +static int toprgu_reset_update(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct mtk_wdt_dev *data = > + container_of(rcdev, struct mtk_wdt_dev, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = readl(data->wdt_base + WDT_SWSYSRST); > + if (assert) > + tmp |= BIT(id); > + else > + tmp &= ~BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->wdt_base + WDT_SWSYSRST); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return toprgu_reset_update(rcdev, id, true); > +} > + > +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return toprgu_reset_update(rcdev, id, false); > +} > + > +static int toprgu_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + int ret; > + > + ret = toprgu_reset_assert(rcdev, id); > + if (ret) > + return ret; > + > + return toprgu_reset_deassert(rcdev, id); > +} > + > +static const struct reset_control_ops toprgu_reset_ops = { > + .assert = toprgu_reset_assert, > + .deassert = toprgu_reset_deassert, > + .reset = toprgu_reset, > +}; > + > +static int toprgu_register_reset_controller(struct platform_device *pdev, > + int rst_num) > +{ > + int ret; > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); > + > + spin_lock_init(&mtk_wdt->lock); > + > + mtk_wdt->rcdev.owner = THIS_MODULE; > + mtk_wdt->rcdev.nr_resets = rst_num; > + mtk_wdt->rcdev.ops = &toprgu_reset_ops; > + mtk_wdt->rcdev.of_node = pdev->dev.of_node; > + ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev); > + if (ret != 0) > + dev_err(&pdev->dev, > + "couldn't register wdt reset controller: %d\n", ret); > + return ret; > +} > + > static int mtk_wdt_restart(struct watchdog_device *wdt_dev, > unsigned long action, void *data) > { > @@ -155,6 +243,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_wdt_dev *mtk_wdt; > + const struct mtk_wdt_data *wdt_data; > int err; > > mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); > @@ -190,6 +279,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) > dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", > mtk_wdt->wdt_dev.timeout, nowayout); > > + wdt_data = of_device_get_match_data(dev); > + if (wdt_data) { > + err = toprgu_register_reset_controller(pdev, > + wdt_data->toprgu_sw_rst_num); > + if (err) > + return err; > + } > return 0; > } > > @@ -219,6 +315,7 @@ static int mtk_wdt_resume(struct device *dev) > > static const struct of_device_id mtk_wdt_dt_ids[] = { > { .compatible = "mediatek,mt6589-wdt" }, > + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); > -- > 2.18.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: Add reset controller 2020-01-10 7:04 [PATCH v11 0/3] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu @ 2020-01-10 7:04 ` Jiaxin Yu 2020-01-13 6:20 ` Nicolas Boichat 2 siblings, 1 reply; 9+ messages in thread From: Jiaxin Yu @ 2020-01-10 7:04 UTC (permalink / raw) To: yong.liang, wim, linux, p.zabel, matthias.bgg, linux-watchdog, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, chang-an.chen, freddy.hsin Cc: yingjoe.chen, sboyd, Jiaxin Yu Add reset controller for 2712. Besides watchdog, MTK toprgu module alsa provide sub-system (eg, audio, camera, codec and connectivity) software reset functionality. Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <groeck7@gmail.com> --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index e88aacb0404d..d6a6393f609d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,6 +9,7 @@ * Based on sunxi_wdt.c */ +#include <dt-bindings/reset-controller/mt2712-resets.h> #include <dt-bindings/reset-controller/mt8183-resets.h> #include <linux/delay.h> #include <linux/err.h> @@ -67,6 +68,10 @@ struct mtk_wdt_data { int toprgu_sw_rst_num; }; +static const struct mtk_wdt_data mt2712_data = { + .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, +}; + static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; @@ -314,6 +319,7 @@ static int mtk_wdt_resume(struct device *dev) #endif static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { /* sentinel */ } -- 2.18.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: Add reset controller 2020-01-10 7:04 ` [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: " Jiaxin Yu @ 2020-01-13 6:20 ` Nicolas Boichat 0 siblings, 0 replies; 9+ messages in thread From: Nicolas Boichat @ 2020-01-13 6:20 UTC (permalink / raw) To: Jiaxin Yu Cc: Yong Liang, wim, linux, Philipp Zabel, Matthias Brugger, linux-watchdog, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support, Devicetree List, chang-an.chen, freddy.hsin, Yingjoe Chen, Stephen Boyd On Fri, Jan 10, 2020 at 3:04 PM Jiaxin Yu <jiaxin.yu@mediatek.com> wrote: > > Add reset controller for 2712. > Besides watchdog, MTK toprgu module alsa provide sub-system (eg, audio, > camera, codec and connectivity) software reset functionality. > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> This is somewhat ok I guess, as Philipp review the same code before you split it into 2 patches. > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: Guenter Roeck <groeck7@gmail.com> Those 2 need to be dropped. > --- > drivers/watchdog/mtk_wdt.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index e88aacb0404d..d6a6393f609d 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -9,6 +9,7 @@ > * Based on sunxi_wdt.c > */ > > +#include <dt-bindings/reset-controller/mt2712-resets.h> > #include <dt-bindings/reset-controller/mt8183-resets.h> > #include <linux/delay.h> > #include <linux/err.h> > @@ -67,6 +68,10 @@ struct mtk_wdt_data { > int toprgu_sw_rst_num; > }; > > +static const struct mtk_wdt_data mt2712_data = { > + .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, > +}; > + > static const struct mtk_wdt_data mt8183_data = { > .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > }; > @@ -314,6 +319,7 @@ static int mtk_wdt_resume(struct device *dev) > #endif > > static const struct of_device_id mtk_wdt_dt_ids[] = { > + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, > { .compatible = "mediatek,mt6589-wdt" }, > { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > { /* sentinel */ } > -- > 2.18.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-01-13 9:20 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-10 7:04 [PATCH v11 0/3] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2020-01-10 7:04 ` [PATCH v11 1/3] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2020-01-13 6:10 ` Nicolas Boichat 2020-01-13 9:12 ` Yong Liang 2020-01-13 9:20 ` Philipp Zabel 2020-01-10 7:04 ` [PATCH v11 2/3] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 2020-01-13 6:19 ` Nicolas Boichat 2020-01-10 7:04 ` [PATCH v11 3/3] watchdog: mtk_wdt: mt2712: " Jiaxin Yu 2020-01-13 6:20 ` Nicolas Boichat
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