linux-wireless.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Ian Molton <ian@mnementh.co.uk>
To: linux-wireless@vger.kernel.org
Cc: arend.vanspriel@broadcom.com, franky.lin@broadcom.com,
	hante.meuleman@broadcom.com
Subject: [PATCH 20/29] brcmfmac: Whitespace patch
Date: Mon, 17 Jul 2017 17:16:28 +0100	[thread overview]
Message-ID: <20170717161637.4652-21-ian@mnementh.co.uk> (raw)
In-Reply-To: <20170717161637.4652-1-ian@mnementh.co.uk>

Improve legibility / conform to kernel coding style.

Signed-off-by: Ian Molton <ian@mnementh.co.uk>
---
 .../wireless/broadcom/brcm80211/brcmfmac/chip.c    | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
index 781f54bb844b..38794d7c1da8 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
@@ -276,29 +276,36 @@ static void brcmf_chip_sb_coredisable(struct brcmf_core *core,
 	base = core->base;
 
 	val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 	if (val & SSB_TMSLOW_RESET)
 		return;
 
 	val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 	if ((val & SSB_TMSLOW_CLOCK) != 0) {
 		/*
 		 * set target reject and spin until busy is clear
 		 * (preserve core-specific bits)
 		 */
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 		ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
 					 val | SSB_TMSLOW_REJECT);
 
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 		udelay(1);
+
 		SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
 			  & SSB_TMSHIGH_BUSY), 100000);
 
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
+
 		if (val & SSB_TMSHIGH_BUSY)
 			brcmf_err("core state still busy\n");
 
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
+
 		if (val & SSB_IDLOW_INITIATOR) {
 			val = ci->ops->read32(ci->ctx,
 					      CORE_SB(base, sbimstate));
@@ -316,16 +323,22 @@ static void brcmf_chip_sb_coredisable(struct brcmf_core *core,
 		/* set reset and reject while enabling the clocks */
 		val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
 		      SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
+
 		ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
+
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 		udelay(10);
 
 		/* clear the initiator reject bit */
 		val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
+
 		if (val & SSB_IDLOW_INITIATOR) {
 			val = ci->ops->read32(ci->ctx,
 					      CORE_SB(base, sbimstate));
+
 			val &= ~SSB_IMSTATE_REJECT;
+
 			ci->ops->write32(ci->ctx,
 					 CORE_SB(base, sbimstate), val);
 		}
@@ -334,6 +347,7 @@ static void brcmf_chip_sb_coredisable(struct brcmf_core *core,
 	/* leave reset and reject asserted */
 	ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
 			 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
+
 	udelay(1);
 }
 
@@ -345,17 +359,20 @@ static void brcmf_chip_ai_coredisable(struct brcmf_core *core,
 
 	/* if core is already in reset, skip reset */
 	regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
+
 	if ((regdata & BCMA_RESET_CTL_RESET) != 0)
 		goto in_reset_configure;
 
 	/* configure reset */
 	ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
 			 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
+
 	ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
 
 	/* put in reset */
 	ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
 			 BCMA_RESET_CTL_RESET);
+
 	usleep_range(10, 20);
 
 	/* wait till reset is 1 */
@@ -366,6 +383,7 @@ static void brcmf_chip_ai_coredisable(struct brcmf_core *core,
 	/* in-reset configure */
 	ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
 			 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
+
 	ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
 }
 
@@ -390,15 +408,19 @@ static void brcmf_chip_sb_resetcore(struct brcmf_core *core, u32 prereset,
 	ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
 			 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
 			 SSB_TMSLOW_RESET);
+
 	regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 	udelay(1);
 
 	/* clear any serror */
 	regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
+
 	if (regdata & SSB_TMSHIGH_SERR)
 		ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
 
 	regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
+
 	if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
 		regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
 		ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
@@ -407,13 +429,17 @@ static void brcmf_chip_sb_resetcore(struct brcmf_core *core, u32 prereset,
 	/* clear reset and allow it to propagate throughout the core */
 	ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
 			 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
+
 	regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 	udelay(1);
 
 	/* leave clock enabled */
 	ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
 			 SSB_TMSLOW_CLOCK);
+
 	regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
+
 	udelay(1);
 }
 
@@ -427,17 +453,23 @@ static void brcmf_chip_ai_resetcore(struct brcmf_core *core, u32 prereset,
 	brcmf_chip_ai_coredisable(core, prereset, reset);
 
 	count = 0;
+
 	while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
 	       BCMA_RESET_CTL_RESET) {
+
 		ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
+
 		count++;
+
 		if (count > 50)
 			break;
+
 		usleep_range(40, 60);
 	}
 
 	ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
 			 postreset | BCMA_IOCTL_CLK);
+
 	ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
 }
 
@@ -908,6 +940,7 @@ static int brcmf_chip_recognition(struct brcmf_chip *ci)
 			brcmf_err("SB chip is not supported\n");
 			return -ENODEV;
 		}
+
 		ci->iscoreup = brcmf_chip_sb_iscoreup;
 		ci->coredisable = brcmf_chip_sb_coredisable;
 		ci->resetcore = brcmf_chip_sb_resetcore;
@@ -915,25 +948,31 @@ static int brcmf_chip_recognition(struct brcmf_chip *ci)
 		core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
 					   SI_ENUM_BASE, 0);
 		brcmf_chip_sb_corerev(ci, core);
+
 		core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
 					   BCM4329_CORE_BUS_BASE, 0);
 		brcmf_chip_sb_corerev(ci, core);
+
 		core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
 					   BCM4329_CORE_SOCRAM_BASE, 0);
 		brcmf_chip_sb_corerev(ci, core);
+
 		core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
 					   BCM4329_CORE_ARM_BASE, 0);
 		brcmf_chip_sb_corerev(ci, core);
 
 		core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
 		brcmf_chip_sb_corerev(ci, core);
+
 		break;
 	case SOCI_AXI:
+
 		ci->iscoreup = brcmf_chip_ai_iscoreup;
 		ci->coredisable = brcmf_chip_ai_coredisable;
 		ci->resetcore = brcmf_chip_ai_resetcore;
 
 		brcmf_chip_dmp_erom_scan(ci);
+
 		break;
 	default:
 		brcmf_err("chip backplane type %u is not supported\n",
@@ -1301,24 +1340,32 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *chip)
 	case BRCM_CC_43241_CHIP_ID:
 	case BRCM_CC_4335_CHIP_ID:
 	case BRCM_CC_4339_CHIP_ID:
+
 		/* read PMU chipcontrol register 3 */
 		addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
 		chip->ops->write32(chip->ctx, addr, 3);
+
 		addr = CORE_CC_REG(pmu->base, chipcontrol_data);
 		reg = chip->ops->read32(chip->ctx, addr);
+
 		return (reg & pmu_cc3_mask) != 0;
 	case BRCM_CC_43430_CHIP_ID:
+
 		addr = CORE_CC_REG(base, sr_control1);
 		reg = chip->ops->read32(chip->ctx, addr);
+
 		return reg != 0;
 	default:
+
 		addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
 		reg = chip->ops->read32(chip->ctx, addr);
+
 		if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
 			return false;
 
 		addr = CORE_CC_REG(pmu->base, retention_ctl);
 		reg = chip->ops->read32(chip->ctx, addr);
+
 		return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
 			       PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
 	}
-- 
2.11.0

  parent reply	other threads:[~2017-07-17 16:48 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-17 16:16 PATCH: brcmfmac driver cleanup Ian Molton
2017-07-17 16:16 ` [PATCH 01/29] brcmfmac: Fix parameter order in brcmf_sdiod_f0_writeb() Ian Molton
2017-07-17 16:16 ` [PATCH 02/29] brcmfmac: Register sizes on hardware are not dependent on compiler types Ian Molton
2017-07-17 16:16 ` [PATCH 03/29] brcmfmac: Split brcmf_sdiod_regrw_helper() up Ian Molton
2017-07-17 16:16 ` [PATCH 04/29] brcmfmac: Clean up brcmf_sdiod_set_sbaddr_window() Ian Molton
2017-07-17 16:16 ` [PATCH 05/29] brcmfmac: Remove dead IO code Ian Molton
2017-07-17 16:16 ` [PATCH 06/29] brcmfmac: Remove bandaid for SleepCSR Ian Molton
2017-07-17 16:16 ` [PATCH 07/29] brcmfmac: Remove brcmf_sdiod_request_data() Ian Molton
2017-07-17 16:16 ` [PATCH 08/29] brcmfmac: Fix uninitialised variable Ian Molton
2017-07-17 16:16 ` [PATCH 09/29] brcmfmac: Remove noisy debugging Ian Molton
2017-07-17 16:16 ` [PATCH 10/29] brcmfmac: Rename bcmerror to err Ian Molton
2017-07-17 16:16 ` [PATCH 11/29] brcmfmac: Split brcmf_sdiod_buffrw function up Ian Molton
2017-07-17 16:16 ` [PATCH 12/29] brcmfmac: Replace old IO functions with simpler ones Ian Molton
2017-07-17 16:16 ` [PATCH 13/29] brcmfmac: Tidy register definitions a little Ian Molton
2017-07-17 16:16 ` [PATCH 14/29] brcmfmac: Remove brcmf_sdiod_addrprep() Ian Molton
2017-07-17 16:16 ` [PATCH 15/29] brcmfamc: remove unnecessary call to brcmf_sdiod_set_backplane_window() Ian Molton
2017-07-17 16:16 ` [PATCH 16/29] brcmfmac: Cleanup offsetof() Ian Molton
2017-07-17 16:16 ` [PATCH 17/29] brcmfmac: Remove unused macro Ian Molton
2017-07-17 16:16 ` [PATCH 18/29] brcmfmac: Rename SOC_AI to SOC_AXI Ian Molton
2017-07-17 16:16 ` [PATCH 19/29] brcmfmac: Get rid of chip_priv and core_priv structs Ian Molton
2017-07-17 16:16 ` Ian Molton [this message]
2017-07-17 16:16 ` [PATCH 21/29] brcmfmac: Simplify chip probe routine Ian Molton
2017-07-17 16:16 ` [PATCH 22/29] brcmfmac: Rename axi functions for clarity Ian Molton
2017-07-17 16:16 ` [PATCH 23/29] brcmfmac: HUGE cleanup of IO access functions Ian Molton
2017-07-17 16:16 ` [PATCH 24/29] brcmfmac: Rename chip.ctx -> chip.bus_priv Ian Molton
2017-07-17 16:16 ` [PATCH 25/29] brcmfmac: Remove repeated calls to brcmf_chip_get_core() Ian Molton
2017-07-17 16:16 ` [PATCH 26/29] brcmfmac: General cleaning up. whitespace and comments fix Ian Molton
2017-07-17 16:16 ` [PATCH 27/29] brcmfmac: Remove {r,w}_sdreg32 Ian Molton
2017-07-17 16:16 ` [PATCH 28/29] brcmfmac: Rename buscore->core for consistency Ian Molton
2017-07-20  7:00   ` kbuild test robot
2017-07-20 17:45     ` Ian Molton
2017-07-17 16:16 ` [PATCH 29/29] brcmfmac: HACK - stabilise the value of ->sbwad in use for some xfer routines Ian Molton

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170717161637.4652-21-ian@mnementh.co.uk \
    --to=ian@mnementh.co.uk \
    --cc=arend.vanspriel@broadcom.com \
    --cc=franky.lin@broadcom.com \
    --cc=hante.meuleman@broadcom.com \
    --cc=linux-wireless@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).