Re: [PATCH v3 2/9] wifi: rtw88: sdio: Add HCI implementation for SDIO based chipsets

[Martin Blumenstingl <martin.blumenstingl@googlemail.com>]

Hello Ping-Ke,

On Thu, Mar 23, 2023 at 3:23 AM Ping-Ke Shih <pkshih@realtek.com> wrote:
[...]
> > +       if (direct) {
> > +               addr = rtw_sdio_to_bus_offset(rtwdev, addr);
> > +               val = rtw_sdio_readl(rtwdev, addr, &ret);
> > +       } else if (addr & 3) {
>
> else if (IS_ALIGNED(addr, 4) {
I'll add these IS_ALIGNED in v4
Also I found an issue with RTW_WCPU_11N devices where indirect read
works differently (those can't use
REG_SDIO_INDIRECT_REG_CFG/REG_SDIO_INDIRECT_REG_DATA but need to go
through the normal path with WLAN_IOREG_OFFSET instead). I'll also
include that fix in v4

[...]
> > +       ret = rtw_register_hw(rtwdev, hw);
> > +       if (ret) {
> > +               rtw_err(rtwdev, "failed to register hw");
> > +               goto err_destroy_txwq;
> > +       }
> > +
>
> Today, people reported there is race condition between register netdev and NAPI
> in rtw89 driver. I wonder if there will be in register netdev and request IRQ.
>
> You can add a msleep(10 * 100) here, and then do 'ifconfig up' and 'iw scan'
> quickly right after SDIO probe to see if it can work well. Otherwise, switching
> the order of rtw_register_hw() and rtw_sdio_request_irq() could be a possible
> solution.
I tried with 1 second and 10 second delays here and could not find any problems.
That said, I am still going to swap the order because a) it seems to
be what most drivers do (ath9k for example) and b) SDIO is a slow bus
and especially slow on my Amlogic SM1 SoC which has some SDIO DMA
errata.
Also testing this made me find another bug during module unregister (I
thought I caught all of them by now) and will include this fix in v4
as well.


As always: thank you for all your inputs!

Best regards,
Martin