From: Tom Psyborg <pozega.tomislav@gmail.com>
To: zhichen@codeaurora.org
Cc: Peter Oh <peter.oh@eero.com>,
linux-wireless@vger.kernel.org, ath10k@lists.infradead.org
Subject: Re: [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices"
Date: Sun, 3 Nov 2019 16:36:03 +0100 [thread overview]
Message-ID: <CAKR_QV+Qh_ErYduYoD8=u_i-y=cbKSJkkajtKxsJ5ML8-Z79EQ@mail.gmail.com> (raw)
In-Reply-To: <8c6d531f6474faf4df55f90185466774@codeaurora.org>
On 30/10/2019, zhichen@codeaurora.org <zhichen@codeaurora.org> wrote:
> On 2019-10-23 01:16, Peter Oh wrote:
>>
>> How can you say value 0 (I believe it's 64 bytes) DMA burst size
>> causes the symptom and 1 fixes it?
>>
>> Peter
>
> Confirmed from HW team that the configuration controls AXI burst size of
> the RD/WR access to the HOST MEM.
> 0- No split , RAW read/write transfer size from MAC is put out on bus as
> burst length.
> 1- Split at 256 byte boundary
> 2,3- Reserved
>
> That's why we see issue with value 0.
>
> Zhi
>
> _______________________________________________
> ath10k mailing list
> ath10k@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/ath10k
>
is this true for both wave1 and wave2 ? at least per this commit
message: ath10k: Fix DMA burst size
it's suppose to be:
0 - 128B max (not sure if this means 128B static, or any size between 0 and 128)
1 - 256B
next prev parent reply other threads:[~2019-11-03 15:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-22 8:57 [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices" Zhi Chen
2019-10-22 10:07 ` Tom Psyborg
2019-10-30 2:44 ` zhichen
2019-11-06 10:01 ` Tom Psyborg
2019-11-07 5:35 ` zhichen
2019-10-22 17:16 ` Peter Oh
2019-10-22 18:24 ` Adrian Chadd
2019-10-30 6:04 ` Peter Oh
2019-10-30 6:28 ` zhichen
2019-10-30 6:16 ` zhichen
2019-10-30 23:01 ` Peter Oh
2019-11-03 15:36 ` Tom Psyborg [this message]
2019-11-04 18:41 ` Peter Oh
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