From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: Willy Tarreau <w@1wt.eu>, Scott Wood <scottwood@freescale.com>,
linuxppc-dev <linuxppc-dev@ozlabs.org>
Subject: [PATCH 02/13] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
Date: Mon, 10 Jan 2011 22:37:48 +0100 [thread overview]
Message-ID: <1294695479-344-3-git-send-email-Joakim.Tjernlund@transmode.se> (raw)
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 18 +++++++++++++++++-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index ba05a57..57858ce 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -197,7 +197,17 @@ label: \
STD_EXCEPTION(0x100, Reset, UnknownException)
/* Machine check */
- STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+ . = 0x200
+MachineCheck:
+ EXCEPTION_PROLOG
+ mfspr r20,DSISR
+ stw r20,_DSISR(r21)
+ mfspr r20,DAR
+ stw r20,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ FINISH_EXCEPTION(MachineCheckException)
/* Data access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
@@ -211,6 +221,8 @@ DataAccess:
mr r5,r20
mfspr r4,DAR
stw r4,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
@@ -249,6 +261,8 @@ Alignment:
EXCEPTION_PROLOG
mfspr r4,DAR
stw r4,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
@@ -433,6 +447,7 @@ DataStoreTLBMiss:
* of the MMU.
*/
2: li r21, 0x00f0
+ mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
@@ -543,6 +558,7 @@ DataTLBError:
* of the MMU.
*/
li r21, 0x00f0
+ mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
--
1.7.3.4
next prev parent reply other threads:[~2011-01-10 21:38 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-10 21:37 [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4 Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 01/13] 8xx: Use a macro to simpliy CPU6 errata code Joakim Tjernlund
2011-01-10 21:37 ` Joakim Tjernlund [this message]
2011-01-10 21:37 ` [PATCH 03/13] 8xx: invalidate non present TLBs Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 04/13] 8xx: Fix CONFIG_PIN_TLB Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 05/13] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 06/13] 8xx: Always pin kernel instruction TLB Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 07/13] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 08/13] 8xx: CPU6 errata make DTLB error too big to fit Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 09/13] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 10/13] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 11/13] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 12/13] 8xx: Optimize ITLBMiss handler Joakim Tjernlund
2011-01-10 21:37 ` [PATCH 13/13] 8xx: Optimize TLB Miss handlers Joakim Tjernlund
2011-01-11 6:09 ` [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4 Willy Tarreau
2011-01-11 8:12 ` Joakim Tjernlund
2011-01-11 20:08 ` Willy Tarreau
2011-01-11 20:27 ` Joakim Tjernlund
[not found] ` <OFEC114402.5A694921-ONC1257815.002CC8F2-C1257815.002D1C7D@LocalDomain>
2011-01-11 10:56 ` Joakim Tjernlund
2011-01-13 20:44 ` Scott Wood
2011-01-13 21:31 ` Joakim Tjernlund
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