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From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: Willy Tarreau <w@1wt.eu>, Scott Wood <scottwood@freescale.com>,
	linuxppc-dev <linuxppc-dev@ozlabs.org>
Subject: [PATCH 09/15] 8xx: Add missing Guarded setting in DTLB Error.
Date: Tue, 14 Jun 2011 15:54:54 +0200	[thread overview]
Message-ID: <1308059700-10839-10-git-send-email-Joakim.Tjernlund@transmode.se> (raw)
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>

only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
 arch/ppc/kernel/head_8xx.S |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 44e79b3..199ede5 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -573,9 +573,15 @@ DARFixed:
 	ori	r21, r21, 1		/* Set valid bit in physical L2 page */
 	DO_8xx_CPU6(0x3b80, r3)
 	mtspr	MD_TWC, r21		/* Load pte table base address */
-	mfspr	r21, MD_TWC		/* ....and get the pte address */
-	lwz	r20, 0(r21)		/* Get the pte */
-
+	mfspr	r20, MD_TWC		/* ....and get the pte address */
+	lwz	r20, 0(r20)		/* Get the pte */
+	/* Insert the Guarded flag into the TWC from the Linux PTE.
+	 * It is bit 27 of both the Linux PTE and the TWC
+	 */
+	rlwimi	r21, r20, 0, 27, 27
+	DO_8xx_CPU6(0x3b80, r3)
+	mtspr	MD_TWC, r21
+	mfspr	r21, MD_TWC		/* get the pte address again */
 	ori	r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 	stw	r20, 0(r21)		/* and update pte in table */
 	xori	r20, r20, _PAGE_RW	/* RW bit is inverted */
-- 
1.7.3.4

  parent reply	other threads:[~2011-06-14 14:05 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-14 13:54 [PATCH 00/15] Backport 8xx TLB to 2.4 Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 01/15] 8xx: Use a macro to simpliy CPU6 errata code Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 02/15] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 03/15] 8xx: invalidate non present TLBs Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 04/15] 8xx: Fix CONFIG_PIN_TLB Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 05/15] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 06/15] 8xx: Always pin kernel instruction TLB Joakim Tjernlund
2011-06-14 16:06   ` Dan Malek
2011-06-14 18:00     ` Joakim Tjernlund
2011-06-14 18:11       ` Dan Malek
2011-06-14 18:19         ` Joakim Tjernlund
2011-06-15  9:21         ` Joakim Tjernlund
     [not found]     ` <OF75A64D65.5ABAA9A9-ONC12578AF.0062124A-C12578AF.0062E416@LocalDomain>
2011-06-15  7:36       ` Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 07/15] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 08/15] 8xx: CPU6 errata make DTLB error too big to fit Joakim Tjernlund
2011-06-14 13:54 ` Joakim Tjernlund [this message]
2011-06-14 13:54 ` [PATCH 10/15] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 11/15] 8xx: Set correct HW pte flags in DTLB Error too Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 12/15] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 13/15] 8xx: Use symbolic constants in TLB asm Joakim Tjernlund
2011-06-14 13:54 ` [PATCH 14/15] 8xx: Optimize ITLBMiss handler Joakim Tjernlund
2011-06-14 13:55 ` [PATCH 15/15] 8xx: Optimize TLB Miss handlers Joakim Tjernlund
2011-06-14 16:11 ` [PATCH 00/15] Backport 8xx TLB to 2.4 Dan Malek
2011-06-14 18:10   ` Joakim Tjernlund
2011-06-14 19:31 ` Willy Tarreau
2011-06-15  7:43   ` Joakim Tjernlund

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