From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH -V5 07/13] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
Date: Mon, 30 Jul 2012 16:52:13 +0530 [thread overview]
Message-ID: <1343647339-25576-8-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1343647339-25576-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 13 ++++++++-----
arch/powerpc/include/asm/page_64.h | 16 ++++++++++++----
arch/powerpc/include/asm/pgtable-ppc64.h | 8 ++++++++
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index fe865fe..d24d484 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -422,6 +422,13 @@ extern void slb_set_size(u16 size);
srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
add rt,rt,rx
+/* 4 bits per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
+#else
+/* Right now we only support 64TB */
+#define SLICE_ARRAY_SIZE 32
+#endif
#ifndef __ASSEMBLY__
@@ -466,11 +473,7 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- /*
- * Right now we support 64TB and 4 bits for each
- * 1TB slice we need 32 bytes for 64TB.
- */
- unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
+ unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 6c9bef4..5635acb 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -78,14 +78,22 @@ extern u64 ppc64_pft_size;
#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
+/* 1 bit per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_MASK_SIZE (PGTABLE_RANG >> 43)
+#else
+/*
+ * Right now we support only 64TB.
+ * IF we change this we will have to change the type
+ * of high_slices
+ */
+#define SLICE_MASK_SIZE 8
+#endif
+
#ifndef __ASSEMBLY__
struct slice_mask {
u16 low_slices;
- /*
- * This should be derived out of PGTABLE_RANGE. For the current
- * max 64TB, u64 should be ok.
- */
u64 high_slices;
};
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 8af1cf2..dea953f 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -32,6 +32,14 @@
#endif
#endif
+#if (PGTABLE_RANGE >> 41) > SLICE_ARRAY_SIZE
+#error PGTABLE_RANGE exceeds SLICE_ARRAY_SIZE
+#endif
+
+#if (PGTABLE_RANGE >> 43) > SLICE_MASK_SIZE
+#error PGTABLE_RANGE exceeds slice_mask high_slices size
+#endif
+
/*
* Define the address range of the kernel non-linear virtual area
*/
--
1.7.10
next prev parent reply other threads:[~2012-07-30 11:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-30 11:22 [PATCH -V5 0/13] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 01/13] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 02/13] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 03/13] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-08-01 4:33 ` Paul Mackerras
2012-08-01 7:23 ` Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 04/13] arch/powerpc: Rename va " Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 05/13] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 06/13] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
2012-08-01 5:16 ` Paul Mackerras
2012-08-01 7:43 ` Aneesh Kumar K.V
2012-07-30 11:22 ` Aneesh Kumar K.V [this message]
2012-08-01 5:18 ` [PATCH -V5 07/13] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Paul Mackerras
2012-08-01 7:45 ` Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 08/13] arch/powerpc: Use the rquired number of VSID bits in slbmte Aneesh Kumar K.V
2012-08-01 5:19 ` Paul Mackerras
2012-07-30 11:22 ` [PATCH -V5 09/13] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 10/13] arch/powerpc: Add 64TB support Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 11/13] arch/powerpc: properly isolate kernel and user proto-VSID Aneesh Kumar K.V
2012-08-01 4:31 ` Paul Mackerras
2012-08-01 7:58 ` Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 12/13] arch/powerpc: Replace open coded CONTEXT_BITS value Aneesh Kumar K.V
2012-08-01 5:29 ` Paul Mackerras
2012-08-01 9:56 ` Aneesh Kumar K.V
2012-07-30 11:22 ` [PATCH -V5 13/13] arch/powerpc: Update VSID allocation documentation Aneesh Kumar K.V
2012-08-01 5:35 ` Paul Mackerras
2012-08-01 10:01 ` Aneesh Kumar K.V
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