From: Gavin Shan <shangw@linux.vnet.ibm.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Gavin Shan <shangw@linux.vnet.ibm.com>
Subject: [PATCH 15/23] powerpc/eeh: I/O chip EEH state retrieval
Date: Thu, 30 May 2013 16:23:57 +0800 [thread overview]
Message-ID: <1369902245-5886-16-git-send-email-shangw@linux.vnet.ibm.com> (raw)
In-Reply-To: <1369902245-5886-1-git-send-email-shangw@linux.vnet.ibm.com>
The patch adds I/O chip backend to retrieve the state for the
indicated PE. While the PE state is temperarily unavailable,
we return the default wait time (1000ms).
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 104 ++++++++++++++++++++++++++++-
1 files changed, 103 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index e24622e..8817c1b 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -125,10 +125,112 @@ static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
return ret;
}
+/**
+ * ioda_eeh_get_state - Retrieve the state of PE
+ * @pe: EEH PE
+ * @state: return value
+ *
+ * The PE's state should be retrieved from the PEEV, PEST
+ * IODA tables. Since the OPAL has exported the function
+ * to do it, it'd better to use that.
+ */
+static int ioda_eeh_get_state(struct eeh_pe *pe, int *state)
+{
+ s64 ret = 0;
+ u8 fstate;
+ u16 pcierr;
+ u32 pe_no;
+ int result;
+ struct pci_controller *hose = pe->phb;
+ struct pnv_phb *phb = hose->private_data;
+
+ /*
+ * Sanity check on PE address. The PHB PE address should
+ * be zero.
+ */
+ if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
+ pr_err("%s: PE address %x out of range [0, %x] "
+ "on PHB#%x\n",
+ __func__, pe->addr, phb->ioda.total_pe,
+ hose->global_number);
+ return EEH_STATE_NOT_SUPPORT;
+ }
+
+ /*
+ * When the PHB has fatal-error, the EEH core will retrieve
+ * the state of the associated PE, which isn't existing.
+ * Actually, the EEH core doesn't care the state. So we
+ * just return normal state to keep EEH core moving forward.
+ */
+ if (pe->type & EEH_PE_PHB) {
+ result = 0;
+ result &= ~EEH_STATE_RESET_ACTIVE;
+ result |= EEH_STATE_MMIO_ACTIVE;
+ result |= EEH_STATE_DMA_ACTIVE;
+ result |= EEH_STATE_MMIO_ENABLED;
+ result |= EEH_STATE_DMA_ENABLED;
+
+ return result;
+ }
+
+ /* Retrieve PE status through OPAL */
+ pe_no = pe->addr;
+ ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
+ &fstate, &pcierr, NULL);
+ if (ret) {
+ pr_err("%s: Failed to get EEH status on "
+ "PHB#%x-PE#%x\n, err=%lld\n",
+ __func__, hose->global_number, pe_no, ret);
+ return EEH_STATE_NOT_SUPPORT;
+ }
+
+ /* Parse result out */
+ result = 0;
+ switch (fstate) {
+ case OPAL_EEH_STOPPED_NOT_FROZEN:
+ result &= ~EEH_STATE_RESET_ACTIVE;
+ result |= EEH_STATE_MMIO_ACTIVE;
+ result |= EEH_STATE_DMA_ACTIVE;
+ result |= EEH_STATE_MMIO_ENABLED;
+ result |= EEH_STATE_DMA_ENABLED;
+ break;
+ case OPAL_EEH_STOPPED_MMIO_FREEZE:
+ result &= ~EEH_STATE_RESET_ACTIVE;
+ result |= EEH_STATE_DMA_ACTIVE;
+ result |= EEH_STATE_DMA_ENABLED;
+ break;
+ case OPAL_EEH_STOPPED_DMA_FREEZE:
+ result &= ~EEH_STATE_RESET_ACTIVE;
+ result |= EEH_STATE_MMIO_ACTIVE;
+ result |= EEH_STATE_MMIO_ENABLED;
+ break;
+ case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
+ result &= ~EEH_STATE_RESET_ACTIVE;
+ break;
+ case OPAL_EEH_STOPPED_RESET:
+ result |= EEH_STATE_RESET_ACTIVE;
+ break;
+ case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
+ result |= EEH_STATE_UNAVAILABLE;
+ if (state)
+ *state = 1000;
+ break;
+ case OPAL_EEH_STOPPED_PERM_UNAVAIL:
+ result |= EEH_STATE_NOT_SUPPORT;
+ break;
+ default:
+ pr_warning("%s: Unexpected EEH status 0x%x "
+ "on PHB#%x-PE#%x\n",
+ __func__, fstate, hose->global_number, pe_no);
+ }
+
+ return result;
+}
+
struct pnv_eeh_ops ioda_eeh_ops = {
.post_init = ioda_eeh_post_init,
.set_option = ioda_eeh_set_option,
- .get_state = NULL,
+ .get_state = ioda_eeh_get_state,
.reset = NULL,
.get_log = NULL,
.configure_bridge = NULL
--
1.7.5.4
next prev parent reply other threads:[~2013-05-30 8:24 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-30 8:23 [PATCH v2 00/23] powerpc/eeh: Enhance converting EEH dev Gavin Shan
2013-05-30 8:23 ` [PATCH 01/23] " Gavin Shan
2013-05-30 8:23 ` [PATCH 02/23] powerpc/eeh: Function to tranverse PCI devices Gavin Shan
2013-06-01 4:13 ` Benjamin Herrenschmidt
2013-06-03 1:00 ` Gavin Shan
2013-05-30 8:23 ` [PATCH 03/23] powerpc/eeh: Make eeh_phb_pe_get() public Gavin Shan
2013-06-01 4:14 ` Benjamin Herrenschmidt
2013-06-03 1:02 ` Gavin Shan
2013-05-30 8:23 ` [PATCH 04/23] powerpc/eeh: Make eeh_pe_get() public Gavin Shan
2013-05-30 8:23 ` [PATCH 05/23] powerpc/eeh: Trace PCI bus from PE Gavin Shan
2013-05-30 8:23 ` [PATCH 06/23] powerpc/eeh: Make eeh_init() public Gavin Shan
2013-05-30 8:23 ` [PATCH 07/23] powerpc/eeh: EEH post initialization operation Gavin Shan
2013-05-30 8:23 ` [PATCH 08/23] powerpc/eeh: Refactor eeh_reset_pe_once() Gavin Shan
2013-06-01 4:18 ` Benjamin Herrenschmidt
2013-06-03 1:03 ` Gavin Shan
2013-05-30 8:23 ` [PATCH 09/23] powerpc/eeh: Delay EEH probe during hotplug Gavin Shan
2013-05-30 8:23 ` [PATCH 10/23] powerpc/eeh: Differentiate EEH events Gavin Shan
2013-05-30 8:23 ` [PATCH 11/23] powerpc/eeh: Sync OPAL API with firmware Gavin Shan
2013-05-30 8:23 ` [PATCH 12/23] powerpc/eeh: EEH backend for P7IOC Gavin Shan
2013-05-30 8:23 ` [PATCH 13/23] powerpc/eeh: I/O chip post initialization Gavin Shan
2013-05-30 8:23 ` [PATCH 14/23] powerpc/eeh: I/O chip EEH enable option Gavin Shan
2013-05-30 8:23 ` Gavin Shan [this message]
2013-05-30 8:23 ` [PATCH 16/23] powerpc/eeh: I/O chip PE reset Gavin Shan
2013-06-01 4:24 ` Benjamin Herrenschmidt
2013-06-03 1:09 ` Gavin Shan
2013-05-30 8:23 ` [PATCH 17/23] powerpc/eeh: I/O chip PE log and bridge setup Gavin Shan
2013-05-30 8:24 ` [PATCH 18/23] powerpc/eeh: PowerNV EEH backends Gavin Shan
2013-06-01 4:29 ` Benjamin Herrenschmidt
2013-06-03 1:10 ` Gavin Shan
2013-05-30 8:24 ` [PATCH 19/23] powerpc/eeh: Initialization for PowerNV Gavin Shan
2013-05-30 8:24 ` [PATCH 20/23] powerpc/eeh: Enable EEH check for config access Gavin Shan
2013-05-30 8:24 ` [PATCH 21/23] powerpc/eeh: Process interrupts caused by EEH Gavin Shan
2013-05-30 8:24 ` [PATCH 22/23] powerpc/eeh: Connect EEH error interrupt handle Gavin Shan
2013-06-01 4:32 ` Benjamin Herrenschmidt
2013-05-30 8:24 ` [PATCH 23/23] powerpc/eeh: Add debugfs entry to inject errors Gavin Shan
2013-06-01 4:34 ` Benjamin Herrenschmidt
2013-06-03 1:23 ` Gavin Shan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1369902245-5886-16-git-send-email-shangw@linux.vnet.ibm.com \
--to=shangw@linux.vnet.ibm.com \
--cc=linuxppc-dev@lists.ozlabs.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).