From: Michael Neuling <mikey@neuling.org>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 2/5] powerpc: Rework setting up H/FSCR bit definitions
Date: Fri, 9 Aug 2013 17:29:28 +1000 [thread overview]
Message-ID: <1376033371-28713-2-git-send-email-mikey@neuling.org> (raw)
In-Reply-To: <1376033371-28713-1-git-send-email-mikey@neuling.org>
In-Reply-To: <25550.1375872955@ale.ozlabs.ibm.com>
This reworks the Facility Status and Control Regsiter (FSCR) config bit
definitions so that we can access the bit numbers. This is needed for a
subsequent patch to fix the userspace DSCR handling.
HFSCR and FSCR bit definitions are the same, so reuse them.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Cc: <stable@vger.kernel.org> [v3.10]
---
arch/powerpc/include/asm/reg.h | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6840e4..99222e2 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -254,19 +254,28 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_TAR_LG 8 /* Enable Target Address Register */
+#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
+#define FSCR_TM_LG 5 /* Enable Transactional Memory */
+#define FSCR_PM_LG 4 /* Enable prob/priv access to PMU SPRs */
+#define FSCR_BHRB_LG 3 /* Enable Branch History Rolling Buffer*/
+#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
+#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
+#define FSCR_FP_LG 0 /* Enable Floating Point */
#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
-#define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
+#define FSCR_TAR __MASK(FSCR_TAR_LG)
+#define FSCR_EBB __MASK(FSCR_EBB_LG)
+#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
-#define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */
-#define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */
-#define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */
-#define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
-#define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
-#define HFSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */
-#define HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX */
-#define HFSCR_FP (1 << (63-63)) /* Enable Floating Point */
+#define HFSCR_TAR __MASK(FSCR_TAR_LG)
+#define HFSCR_EBB __MASK(FSCR_EBB_LG)
+#define HFSCR_TM __MASK(FSCR_TM_LG)
+#define HFSCR_PM __MASK(FSCR_PM_LG)
+#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
+#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
+#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
+#define HFSCR_FP __MASK(FSCR_FP_LG)
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0 (1ul << (63-0))
--
1.8.1.2
next prev parent reply other threads:[~2013-08-09 7:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-07 6:11 [PATCH 1/4] powerpc/tm: Add checkpointed versions of some SPRs to thread_struct Michael Neuling
2013-08-07 6:11 ` [PATCH 2/4] powerpc: Add new save_tar() register function Michael Neuling
2013-08-07 8:07 ` Paul Mackerras
2013-08-07 10:55 ` Michael Neuling
2013-08-08 2:33 ` [PATCH v2 1/4] powerpc/tm: Add checkpointed versions of some SPRs to thread_struct Michael Neuling
2013-08-08 2:33 ` [PATCH v2 2/4] powerpc: Add new save_tar() register function Michael Neuling
2013-08-09 3:43 ` [PATCH v3 " Michael Neuling
2013-08-08 2:33 ` [PATCH v2 3/4] powerpc: Save the TAR register earlier Michael Neuling
2013-08-08 2:33 ` [PATCH v2 4/4] powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR Michael Neuling
2013-08-09 7:29 ` [PATCH 1/5] powerpc: Fix hypervisor facility unavaliable vector number Michael Neuling
2013-08-09 7:29 ` Michael Neuling [this message]
2013-08-09 7:29 ` [PATCH 3/5] powerpc: Fix context switch DSCR on POWER8 Michael Neuling
2013-08-09 7:29 ` [PATCH 4/5] powerpc: Save the TAR register earlier Michael Neuling
2013-08-09 7:29 ` [PATCH 5/5] powerpc/tm: Fix context switching TAR, PPR and DSCR SPRs Michael Neuling
2013-08-07 6:11 ` [PATCH 3/4] powerpc: Save the TAR register earlier Michael Neuling
2013-08-07 6:11 ` [PATCH 4/4] powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR Michael Neuling
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