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From: Vladimir Murzin <murzin.v@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: matt@ozlabs.org, netdev@vger.kernel.org,
	Vladimir Murzin <murzin.v@gmail.com>,
	dborkman@redhat.com, edumazet@google.com, paulus@samba.org,
	davem@davemloft.net
Subject: [RESEND PATCH 1/2] powerpc: net: filter: fix DIVWU instruction opcode
Date: Sat, 21 Sep 2013 09:25:33 +0200	[thread overview]
Message-ID: <1379748334-3313-1-git-send-email-murzin.v@gmail.com> (raw)

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96 	divwu   r9,r10,r9
7d 2a 4b d6 	divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
Acked-by: Matt Evans <matt@ozlabs.org>
---
 arch/powerpc/include/asm/ppc-opcode.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d7fe9f5..c91842c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -218,7 +218,7 @@
 #define PPC_INST_MULLW			0x7c0001d6
 #define PPC_INST_MULHWU			0x7c000016
 #define PPC_INST_MULLI			0x1c000000
-#define PPC_INST_DIVWU			0x7c0003d6
+#define PPC_INST_DIVWU			0x7c000396
 #define PPC_INST_RLWINM			0x54000000
 #define PPC_INST_RLDICR			0x78000004
 #define PPC_INST_SLW			0x7c000030
-- 
1.7.10.4

             reply	other threads:[~2013-09-21  7:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-21  7:25 Vladimir Murzin [this message]
2013-09-21  7:25 ` [RESEND PATCH 2/2] ppc: bpf_jit: support MOD operation Vladimir Murzin
2013-09-22 15:13   ` Matt Evans
2013-09-22 15:35     ` Vladimir Murzin

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