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From: Scott Wood <scottwood@freescale.com>
To: Hongbo Zhang <hongbo.zhang@freescale.com>
Cc: "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	Liu Shengzhou-B36685 <Shengzhou.Liu@freescale.com>
Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
Date: Mon, 16 Dec 2013 12:37:14 -0600	[thread overview]
Message-ID: <1387219034.10013.360.camel@snotra.buserror.net> (raw)
In-Reply-To: <52AEC40C.6000008@freescale.com>

On Mon, 2013-12-16 at 17:12 +0800, Hongbo Zhang wrote:
> On 12/13/2013 01:43 PM, Liu Shengzhou-B36685 wrote:
> >
> >> -----Original Message-----
> >> From: Hongbo Zhang [mailto:hongbo.zhang@freescale.com]
> >> Sent: Thursday, December 12, 2013 5:57 PM
> >> To: Liu Shengzhou-B36685; linuxppc-dev@lists.ozlabs.org; Wood Scott-
> >> B07421
> >> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
> >>
> >> Shengzhou,
> >> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
> >> original wrong elo3-dma-2.dtsi hadn't been merged.
> >> But please pay attention to comments from Scott about my changes of
> >> adding 208 for some interrupts, and take some actions if needed, or
> >> further discussions.
> >>
> >> Below comments form Scott:
> >> "The FSL MPIC binding should be updated to point out how this works.
> >> Technically it's not a change to the binding itself, since it's defined
> >> in terms of register offset, but the explanatory text says "So interrupt
> >> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
> >> not accurate for these new high interrupt numbers."
> >>
> > Hongbo,
> > Could you update FSL MPIC binding as Scott pointed out?
> 
> We only need to add more explanatory text after the sentence Scott 
> pointed out, like:
> "But for some hardwares, the MPIC registers for interrupts are not 
> continuous in address,  in such cases, an offset can be added to the 
> interrupt number to skip the registers which is not for interrupts."
> 
> Scott, is that OK?

Actually, I misread what that sentence actually says, and it's correct
as is -- but not as helpful as it could be.

I'd add this new paragraph instead:

For example, internal interrupt 0 is at offset 0x200 and thus is
interrupt 16 in the device tree.  MSI bank A interrupt 0 is at offset
0x1c00, and thus is interrupt 224.  MPIC v4.3 adds a new discontiguous
address range for internal interrupts, so internal interrupt 160 is at
offset 0x3000, and thus is interrupt 384.

-Scott

      reply	other threads:[~2013-12-16 18:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-11 11:19 [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component Shengzhou Liu
2013-12-11 11:19 ` [PATCH 2/5] powerpc/fsl_pci: add versionless pci compatible Shengzhou Liu
2013-12-11 11:19 ` [PATCH 3/5] powerpc/fsl-booke: Add initial device tree support for T2080/T2081 Shengzhou Liu
2013-12-11 11:19 ` [PATCH 4/5] powerpc/fsl-booke: Add initial T208x QDS board support Shengzhou Liu
2013-12-17 19:57   ` Scott Wood
2013-12-20  6:42     ` Shengzhou.Liu
2013-12-27 22:53       ` Scott Wood
2013-12-11 11:19 ` [PATCH 5/5] powerpc/fsl-booke: Enable T208xQDS board Shengzhou Liu
2013-12-12  9:57 ` [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component Hongbo Zhang
2013-12-13  5:43   ` Shengzhou.Liu
2013-12-16  9:12     ` Hongbo Zhang
2013-12-16 18:37       ` Scott Wood [this message]

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