From: Minghuan Lian <Minghuan.Lian@freescale.com>
To: <linuxppc-dev@lists.ozlabs.org>
Cc: Scott Wood <scottwood@freescale.com>,
Minghuan Lian <Minghuan.Lian@freescale.com>,
Zang Roy-R61911 <r61911@freescale.com>
Subject: [PATCH][v2] powerpc/pci: Fix IMMRBAR address
Date: Mon, 20 Jan 2014 18:54:20 +0800 [thread overview]
Message-ID: <1390215260-28888-1-git-send-email-Minghuan.Lian@freescale.com> (raw)
For PEXCSRBAR, bit 3-0 indicate prefetchable and address type.
So when getting base address, these bits should be masked,
otherwise we may get incorrect base address.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
Change log:
v2:
Use PCI_BASE_ADDRESS_MEM_MASK instead of 0xfffffff0
arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61d..252716d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -868,6 +868,14 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
pci_bus_read_config_dword(hose->bus,
PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
+
+ /*
+ * For PEXCSRBAR, bit 3-0 indicate prefetchable and
+ * address type. So when getting base address, these
+ * bits should be masked
+ */
+ base &= PCI_BASE_ADDRESS_MEM_MASK;
+
return base;
}
#endif
--
1.8.1.2
next reply other threads:[~2014-01-20 10:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-20 10:54 Minghuan Lian [this message]
2014-01-20 15:39 ` [PATCH][v2] powerpc/pci: Fix IMMRBAR address Roy Zang
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