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From: Michael Ellerman <mpe@ellerman.id.au>
To: <linuxppc-dev@ozlabs.org>
Cc: cody@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com
Subject: [PATCH 20/20] powerpc/perf: Fix handling of L3 events with bank == 1
Date: Fri, 14 Mar 2014 16:00:45 +1100	[thread overview]
Message-ID: <1394773245-18328-21-git-send-email-mpe@ellerman.id.au> (raw)
In-Reply-To: <1394773245-18328-1-git-send-email-mpe@ellerman.id.au>

Currently we reject events which have the L3 bank == 1, such as
0x000084918F, because the cache field is non-zero.

However that is incorrect, because although the bank is non-zero, the
value we would write into MMCRC is zero, and so we can count the event.

So fix the check to ignore the bank selector when checking whether the
cache selector is non-zero.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
 arch/powerpc/perf/power8-pmu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 3ad363d..fe2763b 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -325,9 +325,10 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
 		 * HV writable, and there is no API for guest kernels to modify
 		 * it. The solution is for the hypervisor to initialise the
 		 * field to zeroes, and for us to only ever allow events that
-		 * have a cache selector of zero.
+		 * have a cache selector of zero. The bank selector (bit 3) is
+		 * irrelevant, as long as the rest of the value is 0.
 		 */
-		if (cache)
+		if (cache & 0x7)
 			return -1;
 
 	} else if (event & EVENT_IS_L1) {
-- 
1.8.3.2

      parent reply	other threads:[~2014-03-14  5:00 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-14  5:00 powerpc/perf: patches for 3.15 Michael Ellerman
2014-03-14  5:00 ` [PATCH 01/20] powerpc/perf: Make some new raw event codes available in sysfs Michael Ellerman
2014-03-14  5:00 ` [PATCH 02/20] powerpc/perf: Define perf_event_print_debug() to print PMU register values Michael Ellerman
2014-03-14  5:00 ` [PATCH 03/20] powerpc: Add a cpu feature CPU_FTR_PMAO_BUG Michael Ellerman
2014-03-14  5:00 ` [PATCH 04/20] powerpc/perf: Add lost exception workaround Michael Ellerman
2014-03-14  5:00 ` [PATCH 05/20] powerpc/perf: Reject EBB events which specify a sample_type Michael Ellerman
2014-03-14  5:00 ` [PATCH 06/20] powerpc/perf: Clean up the EBB hash defines a little Michael Ellerman
2014-03-14  5:00 ` [PATCH 07/20] powerpc/perf: Avoid mutating event in power8_get_constraint() Michael Ellerman
2014-03-14  5:00 ` [PATCH 08/20] powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBB Michael Ellerman
2014-03-14  5:00 ` [PATCH 09/20] powerpc/perf: Enable BHRB access for EBB events Michael Ellerman
2014-03-14  5:00 ` [PATCH 10/20] sysfs: create bin_attributes under the requested group Michael Ellerman
2014-03-14  5:00 ` [PATCH 11/20] powerpc: Add hvcalls for 24x7 and gpci (Get Performance Counter Info) Michael Ellerman
2014-03-14  5:00 ` [PATCH 12/20] powerpc/perf: Add hv_gpci interface header Michael Ellerman
2014-03-14  5:00 ` [PATCH 13/20] powerpc/perf: Add 24x7 interface headers Michael Ellerman
2014-03-14  5:00 ` [PATCH 14/20] powerpc/perf: Add a shared interface to get gpci version and capabilities Michael Ellerman
2014-03-14  5:00 ` [PATCH 15/20] powerpc/perf: Add macros for defining event fields & formats Michael Ellerman
2014-03-14  5:00 ` [PATCH 16/20] powerpc/perf: Add support for the hv gpci (get performance counter info) interface Michael Ellerman
2014-03-14  5:00 ` [PATCH 17/20] powerpc/perf: Add support for the hv 24x7 interface Michael Ellerman
2014-03-14  5:00 ` [PATCH 18/20] powerpc/perf: Add kconfig option for hypervisor provided counters Michael Ellerman
2014-03-14  5:00 ` [PATCH 19/20] powerpc/perf/hv_{gpci, 24x7}: Add documentation of device attributes Michael Ellerman
2014-03-14  5:00 ` Michael Ellerman [this message]

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