From: Gavin Shan <gwshan@linux.vnet.ibm.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
benh@kernel.crashing.org, mpe@ellerman.id.au, aik@ozlabs.ru,
dja@axtens.net, bhelgaas@google.com, robherring2@gmail.com,
grant.likely@linaro.org, Gavin Shan <gwshan@linux.vnet.ibm.com>
Subject: [PATCH v8 17/45] powerpc/powernv/ioda1: Improve DMA32 segment track
Date: Wed, 17 Feb 2016 14:44:00 +1100 [thread overview]
Message-ID: <1455680668-23298-18-git-send-email-gwshan@linux.vnet.ibm.com> (raw)
In-Reply-To: <1455680668-23298-1-git-send-email-gwshan@linux.vnet.ibm.com>
In current implementation, the DMA32 segments required by one specific
PE isn't calculated with the information hold in the PE independently.
It conflicts with the PCI hotplug design: PE centralized, meaning the
PE's DMA32 segments should be calculated from the information hold in
the PE independently.
This introduces an array (@dma32_segmap) for every PHB to track the
DMA32 segmeng usage. Besides, this moves the logic calculating PE's
consumed DMA32 segments to pnv_pci_ioda1_setup_dma_pe() so that PE's
DMA32 segments are calculated/allocated from the information hold in
the PE (DMA32 weight). Also the logic is improved: we try to allocate
as much DMA32 segments as we can. It's acceptable that number of DMA32
segments less than the expected number are allocated.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/pci-ioda.c | 111 +++++++++++++++++-------------
arch/powerpc/platforms/powernv/pci.h | 7 +-
2 files changed, 66 insertions(+), 52 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 0fc2309..59782fba 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -2007,20 +2007,54 @@ static unsigned int pnv_pci_ioda_total_dma_weight(struct pnv_phb *phb)
}
static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
- struct pnv_ioda_pe *pe,
- unsigned int base,
- unsigned int segs)
+ struct pnv_ioda_pe *pe)
{
struct page *tce_mem = NULL;
struct iommu_table *tbl;
- unsigned int tce32_segsz, i;
+ unsigned int weight, total_weight;
+ unsigned int tce32_segsz, base, segs, i;
int64_t rc;
void *addr;
/* XXX FIXME: Handle 64-bit only DMA devices */
/* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
/* XXX FIXME: Allocate multi-level tables on PHB3 */
+ total_weight = pnv_pci_ioda_total_dma_weight(phb);
+ weight = pnv_pci_ioda_pe_dma_weight(pe);
+
+ segs = (weight * phb->ioda.dma32_count) / total_weight;
+ if (!segs)
+ segs = 1;
+
+ /*
+ * Allocate contiguous DMA32 segments. We begin with the expected
+ * number of segments. With one more attempt, the number of DMA32
+ * segments to be allocated is decreased by one until one segment
+ * is allocated successfully.
+ */
+ while (segs) {
+ for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
+ for (i = base; i < base + segs; i++) {
+ if (phb->ioda.dma32_segmap[i] !=
+ IODA_INVALID_PE)
+ break;
+ }
+
+ if (i >= base + segs)
+ break;
+ }
+
+ if (i >= base + segs)
+ break;
+
+ segs--;
+ }
+
+ if (!segs) {
+ pe_warn(pe, "No available DMA32 segments\n");
+ return;
+ }
tbl = pnv_pci_table_alloc(phb->hose->node);
iommu_register_group(&pe->table_group, phb->hose->global_number,
@@ -2028,6 +2062,8 @@ static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
/* Grab a 32-bit TCE table */
+ pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
+ weight, total_weight, base, segs);
pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
base * PNV_IODA1_DMA32_SEGSIZE,
(base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
@@ -2064,6 +2100,10 @@ static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
}
}
+ /* Setup DMA32 segment mapping */
+ for (i = base; i < base + segs; i++)
+ phb->ioda.dma32_segmap[i] = pe->pe_number;
+
/* Setup linux iommu table */
pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
base * PNV_IODA1_DMA32_SEGSIZE,
@@ -2538,70 +2578,34 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
static void pnv_ioda_setup_dma(struct pnv_phb *phb)
{
struct pci_controller *hose = phb->hose;
- unsigned int weight, total_weight, dma_pe_count;
- unsigned int residual, remaining, segs, base;
struct pnv_ioda_pe *pe;
-
- total_weight = pnv_pci_ioda_total_dma_weight(phb);
- dma_pe_count = 0;
- list_for_each_entry(pe, &phb->ioda.pe_list, list) {
- weight = pnv_pci_ioda_pe_dma_weight(pe);
- if (weight > 0)
- dma_pe_count++;
- }
+ unsigned int weight;
/* If we have more PE# than segments available, hand out one
* per PE until we run out and let the rest fail. If not,
* then we assign at least one segment per PE, plus more based
* on the amount of devices under that PE
*/
- if (dma_pe_count > phb->ioda.tce32_count)
- residual = 0;
- else
- residual = phb->ioda.tce32_count - dma_pe_count;
-
pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
- hose->global_number, phb->ioda.tce32_count);
- pr_info("PCI: %d PE# for a total weight of %d\n",
- dma_pe_count, total_weight);
+ hose->global_number, phb->ioda.dma32_count);
pnv_pci_ioda_setup_opal_tce_kill(phb);
- /* Walk our PE list and configure their DMA segments, hand them
- * out one base segment plus any residual segments based on
- * weight
- */
- remaining = phb->ioda.tce32_count;
- base = 0;
+ /* Walk our PE list and configure their DMA segments */
list_for_each_entry(pe, &phb->ioda.pe_list, list) {
weight = pnv_pci_ioda_pe_dma_weight(pe);
if (!weight)
continue;
- if (!remaining) {
- pe_warn(pe, "No DMA32 resources available\n");
- continue;
- }
- segs = 1;
- if (residual) {
- segs += ((weight * residual) + (total_weight / 2)) /
- total_weight;
- if (segs > remaining)
- segs = remaining;
- }
-
/*
* For IODA2 compliant PHB3, we needn't care about the weight.
* The all available 32-bits DMA space will be assigned to
* the specific PE.
*/
if (phb->type == PNV_PHB_IODA1) {
- pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
- weight, segs);
- pnv_pci_ioda1_setup_dma_pe(phb, pe, base, segs);
+ pnv_pci_ioda1_setup_dma_pe(phb, pe);
} else if (phb->type == PNV_PHB_IODA2) {
pe_info(pe, "Assign DMA32 space\n");
- segs = 0;
pnv_pci_ioda2_setup_dma_pe(phb, pe);
} else if (phb->type == PNV_PHB_NPU) {
/*
@@ -2611,9 +2615,6 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb)
* as the PHB3 TVT.
*/
}
-
- remaining -= segs;
- base += segs;
}
}
@@ -3313,7 +3314,8 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
{
struct pci_controller *hose;
struct pnv_phb *phb;
- unsigned long size, m64map_off, m32map_off, pemap_off, iomap_off = 0;
+ unsigned long size, m64map_off, m32map_off, pemap_off;
+ unsigned long iomap_off = 0, dma32map_off = 0;
const __be64 *prop64;
const __be32 *prop32;
int i, len;
@@ -3398,6 +3400,10 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
+ /* Calculate how many 32-bit TCE segments we have */
+ phb->ioda.dma32_count = phb->ioda.m32_pci_base /
+ PNV_IODA1_DMA32_SEGSIZE;
+
/* Allocate aux data & arrays. We don't have IO ports on PHB3 */
size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
m64map_off = size;
@@ -3407,6 +3413,9 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
if (phb->type == PNV_PHB_IODA1) {
iomap_off = size;
size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
+ dma32map_off = size;
+ size += phb->ioda.dma32_count *
+ sizeof(phb->ioda.dma32_segmap[0]);
}
pemap_off = size;
size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
@@ -3422,6 +3431,10 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
phb->ioda.io_segmap = aux + iomap_off;
for (i = 0; i < phb->ioda.total_pe_num; i++)
phb->ioda.io_segmap[i] = IODA_INVALID_PE;
+
+ phb->ioda.dma32_segmap = aux + dma32map_off;
+ for (i = 0; i < phb->ioda.dma32_count; i++)
+ phb->ioda.dma32_segmap[i] = IODA_INVALID_PE;
}
phb->ioda.pe_array = aux + pemap_off;
set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc);
@@ -3430,7 +3443,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
mutex_init(&phb->ioda.pe_list_mutex);
/* Calculate how many 32-bit TCE segments we have */
- phb->ioda.tce32_count = phb->ioda.m32_pci_base /
+ phb->ioda.dma32_count = phb->ioda.m32_pci_base /
PNV_IODA1_DMA32_SEGSIZE;
#if 0 /* We should really do that ... */
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index e90bcbe..350e630 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -146,6 +146,10 @@ struct pnv_phb {
int *m32_segmap;
int *io_segmap;
+ /* DMA32 segment maps - IODA1 only */
+ unsigned long dma32_count;
+ int *dma32_segmap;
+
/* IRQ chip */
int irq_chip_init;
struct irq_chip irq_chip;
@@ -162,9 +166,6 @@ struct pnv_phb {
*/
unsigned char pe_rmap[0x10000];
- /* 32-bit TCE tables allocation */
- unsigned long tce32_count;
-
/* TCE cache invalidate registers (physical and
* remapped)
*/
--
2.1.0
next prev parent reply other threads:[~2016-02-17 3:45 UTC|newest]
Thread overview: 152+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-17 3:43 [PATCH v8 00/45] powerpc/powernv: PCI hotplug support Gavin Shan
2016-02-17 3:43 ` [PATCH v8 01/45] PCI: Add pcibios_setup_bridge() Gavin Shan
2016-02-17 3:43 ` [PATCH v8 02/45] powerpc/pci: Override pcibios_setup_bridge() Gavin Shan
2016-04-13 5:52 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 03/45] powerpc/pci: Cleanup on struct pci_controller_ops Gavin Shan
2016-02-17 4:18 ` Andrew Donnellan
2016-04-13 5:52 ` Alexey Kardashevskiy
2016-04-19 23:59 ` Gavin Shan
2016-02-17 3:43 ` [PATCH v8 04/45] powerpc/powernv: Cleanup on pci_controller_ops instances Gavin Shan
2016-02-17 4:38 ` Andrew Donnellan
2016-02-17 3:43 ` [PATCH v8 05/45] powerpc/powernv: Drop phb->bdfn_to_pe() Gavin Shan
2016-04-13 5:53 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 06/45] powerpc/powernv: Reorder fields in struct pnv_phb Gavin Shan
2016-04-13 5:56 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 07/45] powerpc/powernv: Rename PE# " Gavin Shan
2016-04-13 5:57 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 08/45] powerpc/powernv: Fix initial IO and M32 segmap Gavin Shan
2016-04-13 6:21 ` Alexey Kardashevskiy
2016-04-13 7:53 ` Gavin Shan
2016-04-13 9:53 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 09/45] powerpc/powernv: Simplify pnv_ioda_setup_pe_seg() Gavin Shan
2016-04-13 6:45 ` Alexey Kardashevskiy
2016-04-20 0:04 ` Gavin Shan
2016-02-17 3:43 ` [PATCH v8 10/45] powerpc/powernv: IO and M32 mapping based on PCI device resources Gavin Shan
2016-02-17 3:43 ` [PATCH v8 11/45] powerpc/powernv: Track M64 segment consumption Gavin Shan
2016-04-13 7:09 ` Alexey Kardashevskiy
2016-04-20 0:05 ` Gavin Shan
2016-02-17 3:43 ` [PATCH v8 12/45] powerpc/powernv: Rename M64 related functions Gavin Shan
2016-04-13 7:20 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 13/45] powerpc/powernv/ioda1: M64 support on P7IOC Gavin Shan
2016-04-13 7:47 ` Alexey Kardashevskiy
2016-04-20 0:22 ` Gavin Shan
2016-04-20 2:55 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 14/45] powerpc/powernv/ioda1: Rename pnv_pci_ioda_setup_dma_pe() Gavin Shan
2016-04-13 7:36 ` Alexey Kardashevskiy
2016-02-17 3:43 ` [PATCH v8 15/45] powerpc/powernv/ioda1: Introduce PNV_IODA1_DMA32_SEGSIZE Gavin Shan
2016-04-13 8:29 ` Alexey Kardashevskiy
2016-04-13 23:54 ` Gavin Shan
2016-04-14 3:36 ` Alexey Kardashevskiy
2016-04-20 0:25 ` Gavin Shan
2016-02-17 3:43 ` [PATCH v8 16/45] powerpc/powernv: Remove DMA32 PE list Gavin Shan
2016-04-13 8:59 ` Alexey Kardashevskiy
2016-04-20 0:34 ` Gavin Shan
2016-02-17 3:44 ` Gavin Shan [this message]
2016-04-19 1:50 ` [PATCH v8 17/45] powerpc/powernv/ioda1: Improve DMA32 segment track Alexey Kardashevskiy
2016-04-20 0:49 ` Gavin Shan
2016-04-20 5:10 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 18/45] powerpc/powernv: Increase PE# capacity Gavin Shan
2016-04-19 2:02 ` Alexey Kardashevskiy
2016-04-20 0:52 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 19/45] powerpc/powernv: Use PE instead of number during setup and release Gavin Shan
2016-04-19 2:50 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 20/45] powerpc/powernv: Allocate PE# in reverse order Gavin Shan
2016-04-19 3:07 ` Alexey Kardashevskiy
2016-04-20 1:04 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 21/45] powerpc/powernv: Create PEs at PCI hot plugging time Gavin Shan
2016-04-19 4:16 ` Alexey Kardashevskiy
2016-04-20 1:12 ` Gavin Shan
2016-04-20 3:00 ` Alexey Kardashevskiy
2016-04-20 3:35 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 22/45] powerpc/powernv/ioda1: Support releasing IODA1 TCE table Gavin Shan
2016-04-19 4:28 ` Alexey Kardashevskiy
2016-04-20 1:15 ` Gavin Shan
2016-04-20 3:17 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 23/45] powerpc/powernv: Dynamically release PEs Gavin Shan
2016-04-19 5:19 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 24/45] powerpc/pci: Rename pcibios_{add, remove}_pci_devices() Gavin Shan
2016-04-19 5:28 ` [PATCH v8 24/45] powerpc/pci: Rename pcibios_{add,remove}_pci_devices() Alexey Kardashevskiy
2016-04-20 1:23 ` Gavin Shan
2016-04-20 3:21 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 25/45] powerpc/pci: Rename pcibios_find_pci_bus() Gavin Shan
2016-04-19 5:31 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 26/45] powerpc/pci: Move pci_find_bus_by_node() around Gavin Shan
2016-02-17 3:44 ` [PATCH v8 27/45] powerpc/pci: Export pci_add_device_node_info() Gavin Shan
2016-04-19 5:35 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 28/45] powerpc/pci: Introduce pci_remove_device_node_info() Gavin Shan
2016-04-19 5:48 ` Alexey Kardashevskiy
2016-04-20 1:25 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 29/45] powerpc/pci: Export pci_traverse_device_nodes() Gavin Shan
2016-04-19 5:51 ` Alexey Kardashevskiy
2016-04-20 1:27 ` Gavin Shan
2016-04-20 3:39 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 30/45] powerpc/pci: Delay populating pdn Gavin Shan
2016-04-19 8:19 ` Alexey Kardashevskiy
2016-04-20 2:13 ` Gavin Shan
2016-04-20 3:54 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 31/45] powerpc/pci: Don't scan empty slot Gavin Shan
2016-04-19 8:19 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 32/45] powerpc/pci: Update bridge windows on PCI plug Gavin Shan
2016-04-19 8:47 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 33/45] powerpc/powernv: Simplify pnv_eeh_reset() Gavin Shan
2016-02-17 4:35 ` Andrew Donnellan
2016-04-19 8:49 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 34/45] powerpc/powernv: Exclude root bus in pnv_pci_reset_secondary_bus() Gavin Shan
2016-04-19 8:57 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 35/45] powerpc/powernv: Fundamental reset " Gavin Shan
2016-04-19 9:04 ` Alexey Kardashevskiy
2016-04-20 1:36 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 36/45] powerpc/powernv: Support PCI slot ID Gavin Shan
2016-04-19 9:28 ` Alexey Kardashevskiy
2016-04-20 2:28 ` Gavin Shan
2016-04-20 4:14 ` Alexey Kardashevskiy
2016-04-22 4:23 ` Alistair Popple
2016-02-17 3:44 ` [PATCH v8 37/45] powerpc/powernv: Use firmware PCI slot reset infrastructure Gavin Shan
2016-04-19 9:34 ` Alexey Kardashevskiy
2016-04-20 2:33 ` Gavin Shan
2016-04-20 4:17 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 38/45] powerpc/powernv: Functions to get/set PCI slot status Gavin Shan
2016-04-19 9:39 ` Alexey Kardashevskiy
2016-04-20 2:36 ` Gavin Shan
2016-04-20 4:25 ` Alexey Kardashevskiy
2016-02-17 3:44 ` [PATCH v8 39/45] powerpc/powernv: Select OF_DYNAMIC Gavin Shan
2016-04-19 9:42 ` Alexey Kardashevskiy
2016-04-20 2:38 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 40/45] drivers/of: Split unflatten_dt_node() Gavin Shan
2016-02-17 14:30 ` Rob Herring
2016-04-20 2:38 ` Gavin Shan
2016-05-02 2:02 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 41/45] drivers/of: Avoid recursively calling unflatten_dt_node() Gavin Shan
2016-02-17 14:53 ` Rob Herring
2016-02-17 3:44 ` [PATCH v8 42/45] drivers/of: Rename unflatten_dt_node() Gavin Shan
2016-02-17 14:59 ` Rob Herring
2016-02-19 3:16 ` Gavin Shan
2016-03-02 2:40 ` Rob Herring
2016-03-08 0:56 ` Gavin Shan
2016-03-17 13:31 ` Rob Herring
2016-03-17 22:44 ` Gavin Shan
2016-02-17 3:44 ` [PATCH v8 43/45] drivers/of: Specify parent node in of_fdt_unflatten_tree() Gavin Shan
2016-02-17 15:00 ` Rob Herring
2016-02-17 15:58 ` Jyri Sarha
2016-02-17 3:44 ` [PATCH v8 44/45] drivers/of: Return allocated memory from of_fdt_unflatten_tree() Gavin Shan
2016-02-17 3:44 ` [PATCH v8 45/45] PCI/hotplug: PowerPC PowerNV PCI hotplug driver Gavin Shan
2016-04-15 0:47 ` Alistair Popple
2016-04-15 1:39 ` Gavin Shan
2016-04-19 10:36 ` Alexey Kardashevskiy
2016-04-20 1:55 ` Alistair Popple
2016-05-02 23:41 ` Gavin Shan
2016-05-03 0:44 ` Alexey Kardashevskiy
2016-05-02 3:44 ` Gavin Shan
2016-05-02 6:11 ` Alexey Kardashevskiy
2016-05-02 23:38 ` Gavin Shan
2016-04-13 7:28 ` [PATCH v8 00/45] powerpc/powernv: PCI hotplug support Alexey Kardashevskiy
2016-04-13 7:42 ` Gavin Shan
2016-04-13 9:14 ` Alexey Kardashevskiy
2016-04-13 23:42 ` Gavin Shan
2016-04-13 23:57 ` Alistair Popple
2016-04-14 1:30 ` Gavin Shan
2016-04-14 3:38 ` Alexey Kardashevskiy
2016-04-15 16:10 ` Rob Herring
2016-04-20 2:40 ` Gavin Shan
2016-04-14 3:26 ` Alexey Kardashevskiy
2016-04-14 5:25 ` Gavin Shan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1455680668-23298-18-git-send-email-gwshan@linux.vnet.ibm.com \
--to=gwshan@linux.vnet.ibm.com \
--cc=aik@ozlabs.ru \
--cc=benh@kernel.crashing.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=dja@axtens.net \
--cc=grant.likely@linaro.org \
--cc=linux-pci@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.au \
--cc=robherring2@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).