From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: linuxppc-dev@ozlabs.org
Subject: [PATCH 08/17] powerpc/powernv/pci: Rename TCE invalidation calls
Date: Mon, 27 Jun 2016 22:25:24 +1000 [thread overview]
Message-ID: <1467030333-31435-9-git-send-email-benh@kernel.crashing.org> (raw)
In-Reply-To: <1467030333-31435-1-git-send-email-benh@kernel.crashing.org>
The TCE invalidation functions are fairly implementation specific,
and while the IODA specs more/less describe the register, in practice
various implementation workarounds may be required. So name the
functions after the target PHB.
Note today and for the foreseeable future, there's a 1:1 relationship
between an IODA version and a PHB implementation. There exist another
variant of IODA1 (Torrent) but we never supported in with OPAL and
never will.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/platforms/powernv/npu-dma.c | 8 ++++----
arch/powerpc/platforms/powernv/pci-ioda.c | 30 +++++++++++++++---------------
arch/powerpc/platforms/powernv/pci.h | 4 +---
3 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index 0459e10..4383a5f 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -180,7 +180,7 @@ long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
return rc;
}
- pnv_pci_ioda2_tce_invalidate_entire(phb, false);
+ pnv_pci_phb3_tce_invalidate_entire(phb, false);
/* Add the table to the list so its TCE cache will get invalidated */
pnv_pci_link_table_and_group(phb->hose->node, num,
@@ -204,7 +204,7 @@ long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
pe_err(npe, "Unmapping failed, ret = %lld\n", rc);
return rc;
}
- pnv_pci_ioda2_tce_invalidate_entire(phb, false);
+ pnv_pci_phb3_tce_invalidate_entire(phb, false);
pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
&npe->table_group);
@@ -270,7 +270,7 @@ static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
0 /* bypass base */, top);
if (rc == OPAL_SUCCESS)
- pnv_pci_ioda2_tce_invalidate_entire(phb, false);
+ pnv_pci_phb3_tce_invalidate_entire(phb, false);
return rc;
}
@@ -334,7 +334,7 @@ void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
pe_err(npe, "Failed to disable bypass, err %lld\n", rc);
return;
}
- pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
+ pnv_pci_phb3_tce_invalidate_entire(npe->phb, false);
}
struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 341a9db..e759900 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1729,7 +1729,7 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
}
}
-static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
+static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
unsigned long index, unsigned long npages, bool rm)
{
struct iommu_table_group_link *tgl = list_first_entry_or_null(
@@ -1790,7 +1790,7 @@ static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
attrs);
if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
- pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
+ pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
return ret;
}
@@ -1803,7 +1803,7 @@ static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
if (!ret && (tbl->it_type &
(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
- pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
+ pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
return ret;
}
@@ -1815,7 +1815,7 @@ static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
pnv_tce_free(tbl, index, npages);
if (tbl->it_type & TCE_PCI_SWINV_FREE)
- pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
+ pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
}
static struct iommu_table_ops pnv_ioda1_iommu_ops = {
@@ -1827,13 +1827,13 @@ static struct iommu_table_ops pnv_ioda1_iommu_ops = {
.get = pnv_tce_get,
};
-#define TCE_KILL_INVAL_ALL PPC_BIT(0)
-#define TCE_KILL_INVAL_PE PPC_BIT(1)
-#define TCE_KILL_INVAL_TCE PPC_BIT(2)
+#define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
+#define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
+#define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
-void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
+void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
{
- const unsigned long val = TCE_KILL_INVAL_ALL;
+ const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
mb(); /* Ensure previous TCE table stores are visible */
if (rm)
@@ -1844,10 +1844,10 @@ void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
}
-static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
+static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
{
/* 01xb - invalidate TCEs that match the specified PE# */
- unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
+ unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
struct pnv_phb *phb = pe->phb;
if (!phb->ioda.tce_inval_reg)
@@ -1857,14 +1857,14 @@ static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
}
-static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
+static void pnv_pci_phb3_tce_invalidate(unsigned pe_number, bool rm,
__be64 __iomem *invalidate, unsigned shift,
unsigned long index, unsigned long npages)
{
unsigned long start, end, inc;
/* We'll invalidate DMA address in PE scope */
- start = TCE_KILL_INVAL_TCE;
+ start = PHB3_TCE_KILL_INVAL_ONE;
start |= (pe_number & 0xFF);
end = start;
@@ -1901,10 +1901,10 @@ static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
* per TCE entry so we have to invalidate
* the entire cache for it.
*/
- pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm);
+ pnv_pci_phb3_tce_invalidate_entire(pe->phb, rm);
continue;
}
- pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
+ pnv_pci_phb3_tce_invalidate(pe->pe_number, rm,
invalidate, tbl->it_page_shift,
index, npages);
}
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 772ad41..3dfa57b 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -205,8 +205,6 @@ extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_ioda3_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
-extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
- __be64 *startp, __be64 *endp, bool rm);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
@@ -226,7 +224,7 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
/* Nvlink functions */
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
-extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
+extern void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
struct iommu_table *tbl);
--
2.7.4
next prev parent reply other threads:[~2016-06-27 12:26 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-27 12:25 [PATCH 00/17] Initial POWER9 XIVE and PHB4 support Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 01/17] powerpc/powernv: Add XICS emulation APIs Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 02/17] powerpc/irq: Add support for HV virtualization interrupts Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 03/17] powerpc/irq: Add mechanism to force a replay of interrupts Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 04/17] powerpc/xics: Add ICP OPAL backend Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 05/17] powerpc/powernv: Add IODA3 PHB type Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 06/17] powerpc/pseries/pci: Remove obsolete SW invalidate Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 07/17] powerpc/opal: Add real mode call wrappers Benjamin Herrenschmidt
2016-06-28 4:18 ` Michael Neuling
2016-06-28 11:37 ` Michael Ellerman
2016-06-28 11:56 ` Benjamin Herrenschmidt
2016-06-27 12:25 ` Benjamin Herrenschmidt [this message]
2016-06-27 12:25 ` [PATCH 09/17] powerpc/powernv/pci: Remove SWINV constants and obsolete TCE code Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 10/17] powerpc/powernv/pci: Rework accessing the TCE invalidate register Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 11/17] powerpc/powernv/pci: Fallback to OPAL for TCE invalidations Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 12/17] powerpc/powernv: set power_save func after the idle states are initialized Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 13/17] powerpc/powernv/pci: Use the device-tree to get available range of M64's Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 14/17] powerpc/powernv/pci: Check status of a PHB before using it Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 15/17] powerpc/pci: Don't try to allocate resources that will be reassigned Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 16/17] powerpc/pci: Reduce log level of PCI I/O space warning Benjamin Herrenschmidt
2016-06-27 12:25 ` [PATCH 17/17] powerpc/pnv/pci: Fix incorrect PE reservation attempt on some 64-bit BARs Benjamin Herrenschmidt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1467030333-31435-9-git-send-email-benh@kernel.crashing.org \
--to=benh@kernel.crashing.org \
--cc=linuxppc-dev@ozlabs.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).