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From: wei.guo.simon@gmail.com
To: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Cc: Michael Ellerman <mpe@ellerman.id.au>,
	Shuah Khan <shuahkh@osg.samsung.com>,
	Anton Blanchard <anton@samba.org>, Cyril Bur <cyrilbur@gmail.com>,
	Anshuman Khandual <khandual@linux.vnet.ibm.com>,
	Simon Guo <wei.guo.simon@gmail.com>,
	Ulrich Weigand <ulrich.weigand@de.ibm.com>,
	Michael Neuling <mikey@neuling.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Kees Cook <keescook@chromium.org>,
	Rashmica Gupta <rashmicy@gmail.com>,
	Khem Raj <raj.khem@gmail.com>, Jessica Yu <jeyu@redhat.com>,
	Jiri Kosina <jkosina@suse.cz>, Miroslav Benes <mbenes@suse.cz>,
	Suraj Jitindar Singh <sjitindarsingh@gmail.com>,
	Chris Smart <chris@distroguy.com>,
	linux-kselftest@vger.kernel.org
Subject: [PATCH v13 11/30] powerpc/ptrace: Enable support for TM SPR state
Date: Thu, 28 Jul 2016 10:57:40 +0800	[thread overview]
Message-ID: <1469674679-8580-12-git-send-email-wei.guo.simon@gmail.com> (raw)
In-Reply-To: <1469674679-8580-1-git-send-email-wei.guo.simon@gmail.com>

From: Anshuman Khandual <khandual@linux.vnet.ibm.com>

This patch enables support for TM SPR state related ELF core
note NT_PPC_TM_SPR based ptrace requests through PTRACE_GETREGSET,
PTRACE_SETREGSET calls. This is achieved through adding a register
set REGSET_TM_SPR in powerpc corresponding to the ELF core note
section added. It implements the get, set and active functions for
this new register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
---
 arch/powerpc/include/uapi/asm/elf.h |   1 +
 arch/powerpc/kernel/ptrace.c        | 143 +++++++++++++++++++++++++++++++++++-
 2 files changed, 143 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index 1549172..e703c64 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -93,6 +93,7 @@
 #define ELF_NFPREG	33	/* includes fpscr */
 #define ELF_NVMX	34	/* includes all vector registers */
 #define ELF_NVSX	32	/* includes all VSX registers */
+#define ELF_NTMSPRREG	3	/* include tfhar, tfiar, texasr */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index c8bf7e9..24a6296 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -66,6 +66,7 @@ struct pt_regs_offset {
 
 #define TVSO(f)	(offsetof(struct thread_vr_state, f))
 #define TFSO(f)	(offsetof(struct thread_fp_state, f))
+#define TSO(f)	(offsetof(struct thread_struct, f))
 
 static const struct pt_regs_offset regoffset_table[] = {
 	GPR_OFFSET_NAME(0),
@@ -1412,7 +1413,136 @@ static int tm_cvsx_set(struct task_struct *target,
 
 	return ret;
 }
-#endif
+
+/**
+ * tm_spr_active - get active number of registers in TM SPR
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks the active number of available
+ * regisers in the transactional memory SPR category.
+ */
+static int tm_spr_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	return regset->n;
+}
+
+/**
+ * tm_spr_get - get the TM related SPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets transactional memory related SPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct {
+ *	u64		tm_tfhar;
+ *	u64		tm_texasr;
+ *	u64		tm_tfiar;
+ * };
+ */
+static int tm_spr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
+	BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
+	BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	/* Flush the states */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* TFHAR register */
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfhar, 0, sizeof(u64));
+
+	/* TEXASR register */
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_texasr, sizeof(u64),
+				2 * sizeof(u64));
+
+	/* TFIAR register */
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfiar,
+				2 * sizeof(u64), 3 * sizeof(u64));
+	return ret;
+}
+
+/**
+ * tm_spr_set - set the TM related SPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets transactional memory related SPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct {
+ *	u64		tm_tfhar;
+ *	u64		tm_texasr;
+ *	u64		tm_tfiar;
+ * };
+ */
+static int tm_spr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
+	BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
+	BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	/* Flush the states */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* TFHAR register */
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfhar, 0, sizeof(u64));
+
+	/* TEXASR register */
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_texasr, sizeof(u64),
+				2 * sizeof(u64));
+
+	/* TFIAR register */
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfiar,
+				 2 * sizeof(u64), 3 * sizeof(u64));
+	return ret;
+}
+#endif	/* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 /*
  * These are our native regset flavors.
@@ -1434,6 +1564,7 @@ enum powerpc_regset {
 	REGSET_TM_CFPR,		/* TM checkpointed FPR registers */
 	REGSET_TM_CVMX,		/* TM checkpointed VMX registers */
 	REGSET_TM_CVSX,		/* TM checkpointed VSX registers */
+	REGSET_TM_SPR,		/* TM specific SPR registers */
 #endif
 };
 
@@ -1490,6 +1621,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
 	},
+	[REGSET_TM_SPR] = {
+		.core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
+	},
 #endif
 };
 
@@ -1737,6 +1873,11 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
 	},
+	[REGSET_TM_SPR] = {
+		.core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
+	},
 #endif
 };
 
-- 
1.8.3.1

  parent reply	other threads:[~2016-07-28  2:59 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-28  2:57 [PATCH v13 00/30] Add new powerpc specific ELF core notes wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 01/30] elf: Add powerpc specific core note sections wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 02/30] powerpc/process: Add the function flush_tmregs_to_thread wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 03/30] powerpc/ptrace: Enable in transaction NT_PRFPREG ptrace requests wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 04/30] powerpc/ptrace: Enable in transaction NT_PPC_VMX " wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 05/30] powerpc/ptrace: Enable in transaction NT_PPC_VSX " wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 06/30] powerpc/ptrace: Adapt gpr32_get, gpr32_set functions for transaction wei.guo.simon
2016-08-04  6:36   ` Daniel Axtens
2016-08-04  8:28     ` Michael Ellerman
2016-08-05  0:30       ` Daniel Axtens
2016-07-28  2:57 ` [PATCH v13 07/30] powerpc/ptrace: Enable support for NT_PPC_CGPR wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 08/30] powerpc/ptrace: Enable support for NT_PPC_CFPR wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 09/30] powerpc/ptrace: Enable support for NT_PPC_CVMX wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 10/30] powerpc/ptrace: Enable support for NT_PPC_CVSX wei.guo.simon
2016-07-28  2:57 ` wei.guo.simon [this message]
2016-07-28  2:57 ` [PATCH v13 12/30] powerpc/ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 13/30] powerpc/ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 14/30] powerpc/ptrace: Enable support for EBB registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 15/30] powerpc/ptrace: Enable support for Performance Monitor registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 16/30] selftests/powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h' wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 17/30] selftests/powerpc: Use the new SPRN_DSCR_PRIV definiton wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 18/30] selftests/powerpc: Add ptrace tests for EBB wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 19/30] selftests/powerpc: Add ptrace tests for GPR/FPR registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 20/30] selftests/powerpc: Add ptrace tests for GPR/FPR registers in TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 21/30] selftests/powerpc: Add ptrace tests for GPR/FPR registers in suspended TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 22/30] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 23/30] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR in TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 24/30] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 25/30] selftests/powerpc: Add ptrace tests for VSX, VMX registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 26/30] selftests/powerpc: Add ptrace tests for VSX, VMX registers in TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 27/30] selftests/powerpc: Add ptrace tests for VSX, VMX registers in suspended TM wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 28/30] selftests/powerpc: Add ptrace tests for TM SPR registers wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 29/30] selftests/powerpc: Add .gitignore file for ptrace executables wei.guo.simon
2016-07-28  2:57 ` [PATCH v13 30/30] selftests/powerpc: Fix a build issue wei.guo.simon

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