From: Roy Pledge <roy.pledge@nxp.com>
To: <linuxppc-dev@lists.ozlabs.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <oss@buserror.net>,
<robin.murphy@arm.com>
Cc: <madalin.bucur@nxp.com>, <roy.pledge@nxp.com>
Subject: [PATCH v3 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC
Date: Mon, 1 May 2017 17:30:09 -0400 [thread overview]
Message-ID: <1493674213-963-8-git-send-email-roy.pledge@nxp.com> (raw)
In-Reply-To: <1493674213-963-1-git-send-email-roy.pledge@nxp.com>
Rework ioremap() for PPC and ARM. The PPC devices require a
non-coherent mapping while ARM will work with a non-cachable/write
combine mapping.
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
---
drivers/soc/fsl/qbman/bman_portal.c | 12 +++++++++---
drivers/soc/fsl/qbman/qman_portal.c | 12 +++++++++---
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/fsl/qbman/bman_portal.c b/drivers/soc/fsl/qbman/bman_portal.c
index 8354d4d..d37f563 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -125,7 +125,14 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+ /* PPC requires a cacheable/non-coherent mapping of the portal */
+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+ /* For ARM we can use write combine mapping. */
+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -133,8 +140,7 @@ static int bman_portal_probe(struct platform_device *pdev)
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
diff --git a/drivers/soc/fsl/qbman/qman_portal.c b/drivers/soc/fsl/qbman/qman_portal.c
index adbaa30..b5463e4 100644
--- a/drivers/soc/fsl/qbman/qman_portal.c
+++ b/drivers/soc/fsl/qbman/qman_portal.c
@@ -265,7 +265,14 @@ static int qman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+ /* PPC requires a cacheable/non-coherent mapping of the portal */
+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+ /* For ARM we can use write combine mapping. */
+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -273,8 +280,7 @@ static int qman_portal_probe(struct platform_device *pdev)
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
--
2.7.4
next prev parent reply other threads:[~2017-05-01 21:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-01 21:30 [PATCH v3 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms Roy Pledge
2017-05-01 21:30 ` [PATCH v3 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations Roy Pledge
2017-05-01 21:30 ` [PATCH v3 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan " Roy Pledge
2017-05-01 21:30 ` [PATCH v3 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan Roy Pledge
2017-05-01 21:30 ` [PATCH v3 04/11] soc/fsl/qbman: Drop set/clear_bits usage Roy Pledge
2017-05-01 21:30 ` [PATCH v3 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check Roy Pledge
2017-05-01 21:30 ` [PATCH v3 06/11] soc/fsl/qbman: Fix ARM32 typo Roy Pledge
2017-05-01 21:30 ` Roy Pledge [this message]
2017-05-01 21:30 ` [PATCH v3 08/11] soc/fsl/qbman: add QMAN_REV32 Roy Pledge
2017-05-01 21:30 ` [PATCH v3 09/11] soc/fsl/qbman: different register offsets on ARM Roy Pledge
2017-05-01 21:30 ` [PATCH v3 10/11] soc/fsl/qbman: Add missing headers " Roy Pledge
2017-05-01 21:30 ` [PATCH v3 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config " Roy Pledge
2017-05-16 5:41 ` [PATCH v3 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms Scott Wood
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1493674213-963-8-git-send-email-roy.pledge@nxp.com \
--to=roy.pledge@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=madalin.bucur@nxp.com \
--cc=oss@buserror.net \
--cc=robin.murphy@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).