From: Christophe Lombard <clombard@linux.vnet.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,
vaibhav@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com
Subject: [PATCH V2] cxl: Fix timebase synchronization status on P9
Date: Thu, 15 Feb 2018 17:52:04 +0100 [thread overview]
Message-ID: <1518713524-1500-1-git-send-email-clombard@linux.vnet.ibm.com> (raw)
The PSL Timebase register is updated by the PSL to maintain the
timebase.
On P9, the Timebase value is only provided by the CAPP as received
the last time a timebase request was performed.
The timebase requests are initiated through the adapter configuration or
application registers.
The specific sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
---
Changelog[v2]
- Missing Signed-off-by
- Spaces required around the ':'
---
drivers/misc/cxl/pci.c | 35 +++++++++++++++++++----------------
drivers/misc/cxl/sysfs.c | 14 ++++++++++++++
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 758842f..270afb5 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -612,8 +612,6 @@ static u64 timebase_read_xsl(struct cxl *adapter)
static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
{
- u64 psl_tb;
- int delta;
unsigned int retry = 0;
struct device_node *np;
@@ -641,20 +639,25 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
- /* Wait until CORE TB and PSL TB difference <= 16usecs */
- do {
- msleep(1);
- if (retry++ > 5) {
- dev_info(&dev->dev, "PSL timebase can't synchronize\n");
- return;
- }
- psl_tb = adapter->native->sl_ops->timebase_read(adapter);
- delta = mftb() - psl_tb;
- if (delta < 0)
- delta = -delta;
- } while (tb_to_ns(delta) > 16000);
-
- adapter->psl_timebase_synced = true;
+ if (cxl_is_power8()) {
+ u64 psl_tb;
+ int delta;
+
+ /* Wait until CORE TB and PSL TB difference <= 16usecs */
+ do {
+ msleep(1);
+ if (retry++ > 5) {
+ dev_info(&dev->dev, "PSL timebase can't synchronize\n");
+ return;
+ }
+ psl_tb = adapter->native->sl_ops->timebase_read(adapter);
+ delta = mftb() - psl_tb;
+ if (delta < 0)
+ delta = -delta;
+ } while (tb_to_ns(delta) > 16000);
+
+ adapter->psl_timebase_synced = true;
+ }
return;
}
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index a8b6d6a..5384c59 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -63,6 +63,20 @@ static ssize_t psl_timebase_synced_show(struct device *device,
{
struct cxl *adapter = to_cxl_adapter(device);
+ /*
+ * On P9, the Timebase value is only updated as a result of
+ * PSL TimeBase command sent to CAPP.
+ */
+ if (cxl_is_power9()) {
+ u64 psl_tb;
+ int delta;
+
+ psl_tb = cxl_p1_read(adapter, CXL_PSL9_Timebase);
+ delta = mftb() - psl_tb;
+ if (delta < 0)
+ delta = -delta;
+ adapter->psl_timebase_synced = true ? tb_to_ns(delta) < 16000 : false;
+ }
return scnprintf(buf, PAGE_SIZE, "%i\n", adapter->psl_timebase_synced);
}
--
2.7.4
next reply other threads:[~2018-02-15 16:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-15 16:52 Christophe Lombard [this message]
2018-02-16 9:41 ` [PATCH V2] cxl: Fix timebase synchronization status on P9 Frederic Barrat
2018-02-16 10:02 ` Vaibhav Jain
2018-02-16 11:20 ` Frederic Barrat
2018-02-16 10:03 ` Vaibhav Jain
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