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[193.116.124.212]) by smtp.gmail.com with ESMTPSA id i13sm4971717pgn.12.2019.05.15.22.04.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 May 2019 22:04:41 -0700 (PDT) Date: Thu, 16 May 2019 15:04:32 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc/book3s/mm: Clear MMU_FTR_HPTE_TABLE when radix is enabled. To: "Aneesh Kumar K.V" , mpe@ellerman.id.au, paulus@samba.org References: <20190514060205.20887-1-aneesh.kumar@linux.ibm.com> In-Reply-To: <20190514060205.20887-1-aneesh.kumar@linux.ibm.com> MIME-Version: 1.0 User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) Message-Id: <1557982690.pk1t7llmyy.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Aneesh Kumar K.V's on May 14, 2019 4:02 pm: > Avoids confusion when printing Oops message like below >=20 > Faulting instruction address: 0xc00000000008bdb4 > Oops: Kernel access of bad area, sig: 11 [#1] > LE PAGE_SIZE=3D64K MMU=3DRadix MMU=3DHash SMP NR_CPUS=3D2048 NUMA PowerN= V >=20 > Either ibm,pa-features or ibm,powerpc-cpu-features can be used to enable = the > MMU features. We don't clear related MMU feature bits there. We use the k= ernel > commandline to determine what translation mode we want to use and clear t= he > HPTE or radix bit accordingly. On LPAR we do have to renable HASH bit if = the > hypervisor can't do radix. Well we have the HPTE feature: the CPU supports hash MMU mode. It's just the the kernel is booted in radix mode. Could make a difference for KVM, if it will support an HPT guest or not. That's all highly theoretical and we have other inconsistencies already in this stuff, I'd just like to try make things a bit better in the long term. Can we just add an early_radix_enabled() in the oops printing code to select radix or hash MMU? > diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c > index b97aee03924f..0fa6cac3fe82 100644 > --- a/arch/powerpc/mm/pgtable.c > +++ b/arch/powerpc/mm/pgtable.c > @@ -77,9 +77,6 @@ static struct page *maybe_pte_to_page(pte_t pte) > =20 > static pte_t set_pte_filter_hash(pte_t pte) > { > - if (radix_enabled()) > - return pte; > - > pte =3D __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); > if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE)= || > cpu_has_feature(CPU_FTR_NOEXECUTE))) { > @@ -110,6 +107,8 @@ static pte_t set_pte_filter(pte_t pte) > =20 > if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) > return set_pte_filter_hash(pte); > + else if (radix_enabled()) > + return pte; > =20 > /* No exec permission in the first place, move on */ > if (!pte_exec(pte) || !pte_looks_normal(pte)) > @@ -140,7 +139,7 @@ static pte_t set_access_flags_filter(pte_t pte, struc= t vm_area_struct *vma, > { > struct page *pg; > =20 > - if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) > + if (mmu_has_feature(MMU_FTR_HPTE_TABLE) || radix_enabled()) > return pte; > =20 > /* So here, we only care about exec faults, as we use them These would still be good cleanup to make the HPTE_TABLE feature independent from radix. Thanks, Nick =