From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To: mpe@ellerman.id.au
Cc: maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v2] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events
Date: Fri, 13 Mar 2020 13:49:07 -0400 [thread overview]
Message-ID: <1584121747-6213-1-git-send-email-atrajeev@linux.vnet.ibm.com> (raw)
Sampled instruction address register (SIER), is a PMU register,
captures architecture state for a given sample. And sier_user_mask
defined in commit 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit
book3s") defines the architected bits that needs to be saved from the SPR.
Currently all of the bits from SIER are saved for EBB events. Patch fixes
this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out().
This will force save only architected bits from the SIER.
Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
Changes in v2:
- Make the commit message more clearer.
arch/powerpc/perf/core-book3s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3086055..48b61cc 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -579,7 +579,7 @@ static void ebb_switch_out(unsigned long mmcr0)
return;
current->thread.siar = mfspr(SPRN_SIAR);
- current->thread.sier = mfspr(SPRN_SIER);
+ current->thread.sier = mfspr(SPRN_SIER) & SIER_USER_MASK;
current->thread.sdar = mfspr(SPRN_SDAR);
current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
--
1.8.3.1
next reply other threads:[~2020-03-13 17:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 17:49 Athira Rajeev [this message]
2020-03-13 18:06 ` [PATCH v2] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events Segher Boessenkool
2020-03-18 12:00 ` Athira Rajeev
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