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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 11sm12312786pfz.91.2020.03.23.00.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2020 00:05:50 -0700 (PDT) Date: Mon, 23 Mar 2020 17:02:06 +1000 From: Nicholas Piggin Subject: Re: [PATCH v4 11/16] powerpc: Enable Prefixed Instructions To: Jordan Niethe , linuxppc-dev@lists.ozlabs.org References: <20200320051809.24332-1-jniethe5@gmail.com> <20200320051809.24332-12-jniethe5@gmail.com> In-Reply-To: <20200320051809.24332-12-jniethe5@gmail.com> MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1584946911.tca3c5485p.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, dja@axtens.net, bala24@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Jordan Niethe's on March 20, 2020 3:18 pm: > From: Alistair Popple >=20 > Prefix instructions have their own FSCR bit which needs to enabled via > a CPU feature. The kernel will save the FSCR for problem state but it > needs to be enabled initially. >=20 > If prefixed instructions are made unavailable by the [H]FSCR, attempting > to use them will cause a facility unavailable exception. Add "PREFIX" to > the facility_strings[]. >=20 > Currently there are no prefixed instructions that are actually emulated > by emulate_instruction() within facility_unavailable_exception(). > However, when caused by a prefixed instructions the SRR1 PREFIXED bit is > set. Prepare for dealing with emulated prefixed instructions by checking > for this bit. >=20 Reviewed-by: Nicholas Piggin > Signed-off-by: Alistair Popple > Signed-off-by: Jordan Niethe > --- > v4: > - Squash "Check for prefixed instructions in > facility_unavailable_exception()" here > - Remove dt parts for now > --- > arch/powerpc/include/asm/reg.h | 3 +++ > arch/powerpc/kernel/traps.c | 1 + > 2 files changed, 4 insertions(+) >=20 > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re= g.h > index 1aa46dff0957..c7758c2ccc5f 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -397,6 +397,7 @@ > #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */ > =20 > /* HFSCR and FSCR bit numbers are the same */ > +#define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */ > #define FSCR_SCV_LG 12 /* Enable System Call Vectored */ > #define FSCR_MSGP_LG 10 /* Enable MSGP */ > #define FSCR_TAR_LG 8 /* Enable Target Address Register */ > @@ -408,11 +409,13 @@ > #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ > #define FSCR_FP_LG 0 /* Enable Floating Point */ > #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ > +#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG) > #define FSCR_SCV __MASK(FSCR_SCV_LG) > #define FSCR_TAR __MASK(FSCR_TAR_LG) > #define FSCR_EBB __MASK(FSCR_EBB_LG) > #define FSCR_DSCR __MASK(FSCR_DSCR_LG) > #define SPRN_HFSCR 0xbe /* HV=3D1 Facility Status & Control Register */ > +#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG) > #define HFSCR_MSGP __MASK(FSCR_MSGP_LG) > #define HFSCR_TAR __MASK(FSCR_TAR_LG) > #define HFSCR_EBB __MASK(FSCR_EBB_LG) > diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c > index 82a3438300fd..a4764b039749 100644 > --- a/arch/powerpc/kernel/traps.c > +++ b/arch/powerpc/kernel/traps.c > @@ -1720,6 +1720,7 @@ void facility_unavailable_exception(struct pt_regs = *regs) > [FSCR_TAR_LG] =3D "TAR", > [FSCR_MSGP_LG] =3D "MSGP", > [FSCR_SCV_LG] =3D "SCV", > + [FSCR_PREFIX_LG] =3D "PREFIX", > }; > char *facility =3D "unknown"; > u64 value; > --=20 > 2.17.1 >=20 >=20 =