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[110.174.173.27]) by smtp.gmail.com with ESMTPSA id z11sm17894138pfk.46.2020.07.28.03.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 03:53:29 -0700 (PDT) Date: Tue, 28 Jul 2020 20:53:23 +1000 From: Nicholas Piggin Subject: Re: [patch 01/15] mm/memory.c: avoid access flag update TLB flush for retried page fault To: linux-arch , Linus Torvalds , Yang Shi References: <20200723211432.b31831a0df3bc2cbdae31b40@linux-foundation.org> <20200724041508.QlTbrHnfh%akpm@linux-foundation.org> <0323de82-cfbd-8506-fa9c-a702703dd654@linux.alibaba.com> <20200727110512.GB25400@gaia> <39560818-463f-da3a-fc9e-3a4a0a082f61@linux.alibaba.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1595932767.wga6c4yy6a.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hillf Danton , mm-commits@vger.kernel.org, Catalin Marinas , Hugh Dickins , Josef Bacik , Will Deacon , Linux-MM , Matthew Wilcox , Johannes Weiner , Yu Xu , Andrew Morton , linuxppc-dev@lists.ozlabs.org, "Kirill A . Shutemov" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Linus Torvalds's message of July 28, 2020 4:37 am: > [ Adding linux-arch, just to make other architectures aware of this issue= too. >=20 > We have a "flush_tlb_fix_spurious_fault()" thing to take care of the > "TLB may contain stale entries, we can't take the same fault over and > over again" situation. >=20 > On x86, it's a no-op, because x86 doesn't do that. x86 will re-walk > the page tables - or possibly just always invalidate the faulting TLB > entry - before taking a fault, so there can be no long-term stale > TLB's. [snip] > It looks like powerpc people at least thought about this, and only > do it if there is a coprocessor. Which sounds a bit confused, but I > don't know the rules. I'm not sure about ppc32 and 64e, I'm almost certain they should do a=20 local flush if anyting, and someone with a good understanding of the=20 ISAs and CPUs might be able to nop it entirely. I agree global can't=20 ever really make sense (except as a default because we have no generic=20 local flush). powerpc/64s reloads translations after taking a fault, so it's fine with=20 a nop here. The quirk is a problem with coprocessor where it's supposed to=20 invalidate the translation after a fault but it doesn't, so we can get a=20 read-only TLB stuck after something else does a RO->RW upgrade on the=20 TLB. Something like that IIRC. Coprocessors have their own MMU which=20 lives in the nest not the core, so you need a global TLB flush to invalidate that thing. Thanks, Nick