From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E507AC2BB84 for ; Mon, 7 Sep 2020 11:37:00 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63048215A4 for ; Mon, 7 Sep 2020 11:36:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63048215A4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csgroup.eu Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BlR861F1SzDqSF for ; Mon, 7 Sep 2020 21:36:54 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=csgroup.eu (client-ip=93.17.236.30; helo=pegase1.c-s.fr; envelope-from=christophe.leroy@csgroup.eu; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=csgroup.eu Received: from pegase1.c-s.fr (pegase1.c-s.fr [93.17.236.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BlR5Y1dqPzDq8F for ; Mon, 7 Sep 2020 21:34:36 +1000 (AEST) Received: from localhost (mailhub1-int [192.168.12.234]) by localhost (Postfix) with ESMTP id 4BlR5D1g5Lz9tyWL; Mon, 7 Sep 2020 13:34:24 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [192.168.12.234]) (amavisd-new, port 10024) with ESMTP id Ctq1O-PMeJrk; Mon, 7 Sep 2020 13:34:24 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 4BlR5D02Mtz9tyVw; Mon, 7 Sep 2020 13:34:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 54F978B78A; Mon, 7 Sep 2020 13:34:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id KKRC9ZEAhtlF; Mon, 7 Sep 2020 13:34:29 +0200 (CEST) Received: from [10.0.2.15] (unknown [192.168.4.90]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 129A48B77F; Mon, 7 Sep 2020 13:34:29 +0200 (CEST) Subject: Re: [RFC PATCH 02/12] powerpc: remove arguments from interrupt handler functions From: Christophe Leroy To: Nicholas Piggin In-Reply-To: References: <20200905174335.3161229-1-npiggin@gmail.com> <20200905174335.3161229-3-npiggin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: CS Group France Date: Mon, 07 Sep 2020 11:34:17 +0000 Message-ID: <1599478457.27656.1.camel@po17688vm.idsi0.si.c-s.fr> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-37.el6) Content-Transfer-Encoding: 8bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, 2020-09-07 at 11:20 +0200, Christophe Leroy wrote: > > Le 05/09/2020 à 19:43, Nicholas Piggin a écrit : > > Make interrupt handlers all just take the pt_regs * argument and load > > DAR/DSISR etc from that. Make those that return a value return long. > > I like this, it will likely simplify a bit the VMAP_STACK mess. > > Not sure it is that easy. My board is stuck after the start of init. > > > On the 8xx, on Instruction TLB Error exception, we do > > andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ > > On book3s/32, on ISI exception we do: > andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ > > On 40x and bookE, on ISI exception we do: > li r5,0 /* Pass zero as arg3 */ > > > And regs->dsisr will just contain nothing > > So it means we should at least write back r5 into regs->dsisr from there > ? The performance impact should be minimal as we already write _DAR so > the cache line should already be in the cache. > > A hacky 'stw r5, _DSISR(r1)' in handle_page_fault() does the trick, > allthough we don't want to do it for both ISI and DSI at the end, so > you'll have to do it in every head_xxx.S To get you series build and work, I did the following hacks: diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h index acfcc7d5779b..c11045d3113a 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -93,7 +93,9 @@ static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct inter { nmi_exit(); +#ifdef CONFIG_PPC64 this_cpu_set_ftrace_enabled(state->ftrace_enabled); +#endif #ifdef CONFIG_PPC_BOOK3S_64 /* Check we didn't change the pending interrupt mask. */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index f4d0af8e1136..66f7adbe1076 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -663,6 +663,7 @@ ppc_swapcontext: */ .globl handle_page_fault handle_page_fault: + stw r5,_DSISR(r1) addi r3,r1,STACK_FRAME_OVERHEAD #ifdef CONFIG_PPC_BOOK3S_32 andis. r0,r5,DSISR_DABRMATCH@h --- Christophe