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Thu, 8 Oct 2020 10:52:16 +0000 (GMT) From: Athira Rajeev To: mpe@ellerman.id.au Subject: [PATCH 3/4] powerpc/perf: Use the address from SIAR register to set cpumode flags Date: Thu, 8 Oct 2020 06:52:08 -0400 Message-Id: <1602154329-2092-4-git-send-email-atrajeev@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602154329-2092-1-git-send-email-atrajeev@linux.vnet.ibm.com> References: <1602154329-2092-1-git-send-email-atrajeev@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-10-08_07:2020-10-08, 2020-10-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxscore=0 mlxlogscore=924 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2010080077 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" While setting the processor mode for any sample, `perf_get_misc_flags` expects the privilege level to differentiate the userspace and kernel address. On power10 DD1, there is an issue that causes [MSR_HV MSR_PR] bits of Sampled Instruction Event Register (SIER) not to be set for marked events. Hence add a check to use the address in Sampled Instruction Address Register (SIAR) to identify the privilege level. Signed-off-by: Athira Rajeev --- arch/powerpc/perf/core-book3s.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index d766090..c018004 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -250,11 +250,25 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs) static inline u32 perf_get_misc_flags(struct pt_regs *regs) { bool use_siar = regs_use_siar(regs); + unsigned long mmcra = regs->dsisr; + int marked = mmcra & MMCRA_SAMPLE_ENABLE; if (!use_siar) return perf_flags_from_msr(regs); /* + * Check the address in SIAR to identify the + * privilege levels since the SIER[MSR_HV, MSR_PR] + * bits are not set for marked events in power10 + * DD1. + */ + if (marked && (ppmu->flags & PPMU_P10_DD1)) { + if (is_kernel_addr(mfspr(SPRN_SIAR))) + return PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_USER; + } + + /* * If we don't have flags in MMCRA, rather than using * the MSR, we intuit the flags from the address in * SIAR which should give slightly more reliable -- 1.8.3.1