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From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To: mpe@ellerman.id.au
Cc: mikey@neuling.org, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 4/4] powerpc/perf: Exclude kernel samples while counting events in user space.
Date: Thu,  8 Oct 2020 06:52:09 -0400
Message-ID: <1602154329-2092-5-git-send-email-atrajeev@linux.vnet.ibm.com> (raw)
In-Reply-To: <1602154329-2092-1-git-send-email-atrajeev@linux.vnet.ibm.com>

By setting exclude_kernel for user space profiling, we set the
freeze bits in Monitor Mode Control Register. Due to hardware
limitation, sometimes, Sampled Instruction Address register (SIAR)
captures kernel address even when counter freeze bits are set in
Monitor Mode Control Register (MMCR2). Patch adds a check to drop
these samples at such conditions.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
 arch/powerpc/perf/core-book3s.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index c018004..10a2d1f 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2143,6 +2143,18 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
 	perf_event_update_userpage(event);
 
 	/*
+	 * Setting exclude_kernel will only freeze the
+	 * Performance Monitor counters and we may have
+	 * kernel address captured in SIAR. Hence drop
+	 * the kernel sample captured during user space
+	 * profiling. Setting `record` to zero will also
+	 * make sure event throlling is handled.
+	 */
+	if (event->attr.exclude_kernel && record)
+		if (is_kernel_addr(mfspr(SPRN_SIAR)))
+			record = 0;
+
+	/*
 	 * Finally record data if requested.
 	 */
 	if (record) {
-- 
1.8.3.1


      parent reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08 10:52 [PATCH 0/4] powerpc/perf: Power PMU fixes for power10 DD1 Athira Rajeev
2020-10-08 10:52 ` [PATCH 1/4] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" " Athira Rajeev
2020-10-08 10:52 ` [PATCH 2/4] powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID] Athira Rajeev
2020-10-08 10:52 ` [PATCH 3/4] powerpc/perf: Use the address from SIAR register to set cpumode flags Athira Rajeev
2020-10-08 10:52 ` Athira Rajeev [this message]

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