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Date: Tue, 10 Nov 2020 18:49:50 +1000
From: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [RFC PATCH 0/9] powerpc/64s: fast interrupt exit
To: Christophe Leroy <christophe.leroy@csgroup.eu>,
 linuxppc-dev@lists.ozlabs.org
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Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
>=20
>=20
> Le 06/11/2020 =C3=A0 16:59, Nicholas Piggin a =C3=A9crit=C2=A0:
>> This series attempts to improve the speed of interrupts and system calls
>> in two major ways.
>>=20
>> Firstly, the SRR/HSRR registers do not need to be reloaded if they were
>> not used or clobbered fur the duration of the interrupt.
>>=20
>> Secondly, an alternate return location facility is added for soft-masked
>> asynchronous interrupts and then that's used to set everything up for
>> return without having to disable MSR RI or EE.
>>=20
>> After this series, the entire system call / interrupt handler fast path
>> executes no mtsprs and one mtmsrd to enable interrupts initially, and
>> the system call vectored path doesn't even need to do that.
>=20
> Interesting series.
>=20
> Unfortunately, can't be done on PPC32 (at least on non bookE), because it=
 would mean mapping kernel=20
> at 0 instead of 0xC0000000. Not sure libc would like it, and anyway it wo=
uld be an issue for=20
> catching NULL pointer dereferencing, unless we use page tables instead of=
 BATs to map kernel mem,=20
> which would be serious performance cut.

Hmm, why would you have to map at 0?

PPC32 doesn't have soft mask interrupts, but you could still test all=20
MSR[PR]=3D0 interrupts to see if they land inside some region to see if
they hit in the restart table I think?

Could PPC32 skip the SRR reload at least? That's simpler.

Thanks,
Nick